Abstract: A technique for storing accurate operating current values using programmable elements on memory devices. More specifically, programmable elements, such as antifuses, located on a memory device are programmed with measured operating current values corresponding to the memory device, during fabrication. The memory device may be incorporated into a memory module that is incorporated into a system. Once the memory module is incorporated into a system, the programmable elements may be accessed such that the system can be configured to optimally operate in accordance with the operating current values measured for each memory device in the system.

Abstract: Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.

Abstract: Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating current values for specific memory devices on the memory module or a specific lot in which the memory devices are fabricated may be stored on a non-volatile memory device on the memory module. A system may be configured in accordance with the operating current values stored on the non-volatile memory device such that operating current thresholds are not exceeded.

Abstract: Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on the memory modules are accessed from a database such that the operating current values may be implemented to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating current values corresponding to the specific memory devices on the memory module may be stored in a database and accessed during fabrication or during implementation of the memory modules in a system. System performance may be optimized by implementing the unique operating current values corresponding to the specific memory devices on the memory modules.

Abstract: An apparatus and method for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.

Abstract: A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is refreshed during the wait state following issuance of the transition command. Conducting this refresh during this existing wait state eliminates both the concern as to whether rows have been refreshed within the mandated refresh interval and the time required to execute an auto-refresh of at least one row upon completion of the transition.

Abstract: A memory module for an electronic device provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

Abstract: A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bits is used to enable a data strobe preamble as either a default data strobe preamble of the memory or as a reduced data strobe preamble with a time length set equal to a fraction of the default preamble or a fraction of a clock cycle. The enabling bit can be used to provide a input for generating a delay that provides a delayed signal to drivers of the memory for producing a reduced data strobe preamble and for sequencing or driving data to be read out of the memory. The reduced data strobe preamble can also be used for writing data into the memory.

Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

Abstract: A method and apparatus are provided for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bits is used to enable a data strobe preamble as either a default data strobe preamble of the memory or as a reduced data strobe preamble with a time length set equal to a fraction of the default preamble or a fraction of a clock cycle. The enabling bit can be used to provide a input for generating a delay that provides a delayed signal to drivers of the memory for producing a reduced data strobe preamble and for sequencing or driving data to be read out of the memory. The reduced data strobe preamble can also be used for writing data into the memory.

Abstract: A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is refreshed during the wait state following issuance of the transition command. Conducting this refresh during this existing wait state eliminates both the concern as to whether rows have been refreshed within the mandated refresh interval and the time required to execute an auto-refresh of at least one row upon completion of the transition.

Abstract: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

Abstract: A memory module for an electronic device provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

Abstract: An apparatus and method for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.

Abstract: A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is refreshed during the wait state following issuance of the transition command. Conducting this refresh during this existing wait state eliminates both the concern as to whether rows have been refreshed within the mandated refresh interval and the time required to execute an auto-refresh of at least one row upon completion of the transition.

Abstract: A method and apparatus are provided for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bits is used to enable a data strobe preamble as either a default data strobe preamble of the memory or as a reduced data strobe preamble with a time length set equal to a fraction of the default preamble or a fraction of a clock cycle. The enabling bit can be used to provide a input for generating a delay that provides a delayed signal to drivers of the memory for producing a reduced data strobe preamble and for sequencing or driving data to be read out of the memory. The reduced data strobe preamble can also be used for writing data into the memory.

Abstract: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

Abstract: A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is refreshed during the wait state following issuance of the transition command. Conducting this refresh during this existing wait state eliminates both the concern as to whether rows have been refreshed within the mandated refresh interval and the time required to execute an auto-refresh of at least one row upon completion of the transition.