Abstract: A semiconductor device includes a semiconductor substrate including a corrugated surface. A body has a first conductivity type and includes a portion extending continuously along the corrugated surface. A gate dielectric layer is on the body and extends continuously along the corrugated surface. A gate is on the gate dielectric layer, the gate extending continuously along the corrugated surface. A corrugated conformal drift region has a second conductivity type opposite from the first conductivity type, and is on and conformal with the corrugated surface of the semiconductor substrate, and extends continuously along the corrugated surface. A source has the second conductivity type and includes a portion extending continuously along the corrugated surface, the source being in contact with the body. A drain contact region electrically coupled to the drift region and having the second conductivity type.

Abstract: In some examples, an integrated circuit comprises: a semiconductor die including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a metallization structure encapsulated in the dielectric layer, in which the semiconductor substrate includes a transistor having a first current terminal, a second current terminal, and a channel region between the first and second current terminals, and the dielectric layer has a sensing side facing away from the semiconductor substrate; an insulation layer on the sensing side; a sensor terminal on the sensing side and over the channel region; and a restriction structure including an opening and a rigid silicon-based fluidic structure, in which the silicon-based fluidic structure is on the sensing side and encapsulates a fluid cavity on the sensing side, the sensor terminal is in the fluid cavity, and the restriction structure is configured to transport a fluid by microfluidic diffusion.

Abstract: An example microelectromechanical structures (MEMS) switch includes a body having a first end and a second end opposite the first end. The body extends from a base at the first end and has a first width. The MEMS switch further includes a bridge extending laterally from the body at the second end, and a spine extending between the bridge and the base. The spine has a second width smaller than the first width. At least one of the spine or the body includes a first material with a first thermal coefficient and a second material with a second thermal coefficient different from the first thermal coefficient.

Abstract: An apparatus includes first and second electrodes separated by an insulative material (such as a piezoelectric material). The apparatus also includes a protective layer over the first and second electrodes. The protective layer has a first opening that exposes a portion of the first electrode and a second opening that exposes a portion of the second electrode. The apparatus further includes a first electrical contact at least partially within the first opening and electrically coupled to the first electrode. In addition, the apparatus includes a second electrical contact at least partially within the second opening and electrically coupled to the second electrode. Each of the first and second electrical contacts includes a stack of metal layers. The stack of metal layers includes a titanium nitride layer, a titanium layer over the titanium nitride layer, and an aluminum copper layer over the titanium nitride layer and the titanium layer.

Abstract: An apparatus includes first and second electrodes separated by an insulative material (such as a piezoelectric material). The apparatus also includes a protective layer over the first and second electrodes. The protective layer has a first opening that exposes a portion of the first electrode and a second opening that exposes a portion of the second electrode. The apparatus further includes a first electrical contact at least partially within the first opening and electrically coupled to the first electrode. In addition, the apparatus includes a second electrical contact at least partially within the second opening and electrically coupled to the second electrode. Each of the first and second electrical contacts includes a stack of metal layers. The stack of metal layers includes a titanium nitride layer, a titanium layer over the titanium nitride layer, and an aluminum copper layer over the titanium nitride layer and the titanium layer.

Abstract: An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.

Abstract: An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).

Abstract: A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.

Abstract: A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.

Abstract: An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).

Abstract: A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.

Abstract: A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.

Abstract: An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.

Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.

Abstract: Methods (200) and systems (108) are provided for reading data from ferroelectric memory cells (106) in which charge is removed from a sense amp input (SABL/SABLB) prior to application of a plateline signal (PL) to the target cell capacitor (CFE). Where the sense amp input (SABL/SABLB) is initially precharged to zero volts, the extraction of charge provides a negative voltage on the data bitline (BL/BLB) when the plateline signal (PL) is applied, allowing adequate voltage to be applied across the cell capacitor (CFE) together with reduced plateline voltages (PL).

Abstract: The present invention provides a ferroelectric capacitor, a method for manufacture therefor, and a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, may include a first electrode layer (162) located over a substrate (110), wherein the first electrode layer (162) includes iridium, and an oxide electrode template (164) located over the first electrode layer (162). The ferroelectric capacitor (100) may further include a ferroelectric dielectric layer (165) located over the oxide electrode template (164), and a second electrode layer (170) located over the ferroelectric dielectric layer (165).

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.