Abstract: A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

Abstract: Integrated circuit structures comprising an embedded ferroelectric memory cell and methods of forming the same are described. These structures include a transistor level, a ferroelectric device level, a first metal level, an inter-level dielectric level and a second metal level. In a first embodiment, the ferroelectric device level is disposed over an isolation layer of the transistor level and an isolation layer of the ferroelectric level has one or more vias that are laterally sized larger than corresponding contact vias extending through the transistor isolation layer and aligned therewith. In a second embodiment, the first metal level and the ferroelectric device level are integrated into the same level. In a third embodiment, the ferroelectric device level is disposed over the first metal level. In a fourth embodiment, the ferroelectric device level is disposed over the inter-level dielectric level that, in turn, is disposed over the first metal level.

Abstract: A capacitor (100) with a high dielectric constant oxide dielectric (102) plus Ir- or Ir and Rh bond over the oxygen site in Barium strontium titanate (BST) dielectric to achieve the high Schottky barrier, and very thin layers of Ir or Rh with conductive oxide backing layers (106, 116) provide oxygen depletion deterrence. Rh-containing capacitor plates (104, 114) yielding high Schottky barrier interfaces.

Abstract: An embodiment of the instant invention is a method of forming a conductive barrier layer on a dielectric layer, the method comprising the steps of: providing the dielectric layer (112 of FIG. 7d) having a top surface, a bottom surface, and an opening extending from the top surface to the bottom surface, and including a conductive plug (704 of FIG.

Abstract: An embodiment of the instant invention is a method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides, the method comprising the steps of: depositing a first conductive material (114 of FIG. 7d) on the top surface of the dielectric layer and in the opening in the dielectric layer to substantially fill the opening with the conductive material; removing the portion of the first conductive material located on the dielectric layer and removing a portion of the first conductive material located in the opening in the dielectric layer to recess (406 of FIG. 7d) the first conductive material below the top surface of the dielectric layer; depositing a second conductive material (704 of FIG. 7d) in the recess to form a substantially planar top surface substantially coplanar with the top surface of the dielectric layer; and forming a third conductive material (302 of FIG.

Abstract: The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower (32-36) electrodes. The lower electrode comprises a polysilicon base (32), a diffusion barrier (34) on the sidewalls of the polysilicon base (32) and an oxygen stable material (36) on the sidewalls adjacent the diffusion barrier (34) and separated from the polysilicon base (32) sidewalls by the diffusion barrier (34). The oxygen stable material (36) is formed on the sidewalls by a deposition and either etchback or CMP process rather than by a patterned etch. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).

Abstract: A capacitor structure and method. The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower electrodes. The lower electrode comprises a capacitor via (19), diffusion barrier (34) and an oxygen stable material (36). The diffusion barrier (34) is formed over the capacitor via (19) and bitline via (17). The bitline structure (20) is then formed. Next, a multi-level dielectric (80,84) is formed and storage node areas (70)are etched through the multi-level dielectric leaving dielectric sidewalls (66) on the bitline structure (20). The oxygen stable material (36) is then formed in the storage node area (70). Portions of the multi-level dielectric layer (84) over the bitline structure (20) are removed. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).

Abstract: A capacitor structure and method. The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower electrodes. The lower electrode comprises polysilicon(31-32), a diffusion barrier (34) on the polysilicon and an oxygen stable material (36) on the diffusion barrier (34). The oxygen stable material (36) is formed by first forming a disposable dielectric layer (50) patterned and etched to expose the area where the storage node is desired and then depositing the oxygen stable material (36). The oxygen stable material (36) is then either etched back or CMP processed using the disposable dielectric layer (50) as an endpoint. The disposable dielectric layer (50) is then removed. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).

Abstract: A capacitive structure on an integrated circuit and a method of making the same are disclosed, which is particularly useful in random-access memory devices. Generally, the method of the present invention comprises the steps of forming a substantially vertical temporary support 54 (preferably by forming a cylindrical aperture in an insulating layer) on a semiconductor substrate 10 and forming a substantially vertical dielectric film 32 (preferably a high dielectric constant perovskite-phase dielectric film, and more preferably barium strontium titanate) on temporary support 54. The method further comprises depositing a first conductive (e.g. platinum) electrode 60 on substantially vertical dielectric film 32, and subsequently replacing temporary support 54 with a second conductive (e.g. platinum) electrode 64, such that a thin film capacitor 44 which is substantially vertical with respect to substrate 10 is formed.

Abstract: A capacitor structure and method. The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower electrodes. The lower electrode comprises polysilicon(31-32), a diffusion barrier (34) on the polysilicon and an oxygen stable material (36) on the diffusion barrier (34). The diffusion barrier (34) is deposited followed by the deposition of a temporary dielectric layer (50). The temporary dielectric layer (50) is then patterned and etched to expose the area where the storage node is desired. Next, the oxygen stable material (36) is deposited. The oxygen stable material (36) is then either etched back or CMP processed using the temporary dielectric layer (50) as an endpoint. The temporary dielectric layer (50) is then removed along with the exposed portions of diffusion barrier (34). The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).