Abstract: The present invention relates to a metal single crystal in which a metal element is substituted, wherein a metal element A is doped with a metal element B different from the metal element A to form A1-XBX, and a mixed single crystal is formed therefrom by high temperature melting (wherein the metal element A is any one of silver, copper, platinum and gold; the metal element B is any one of silver, copper, platinum and gold; and 0.01?x?0.09). Therefore, a metal single crystal, which is a mixed crystal with more superior electrical properties than a conventional metal, is formed by doping a metal with excellent electrical properties with a metal element different from the metal, and growing the doped metal into a mixed crystal.

Abstract: The present invention provides a heat transfer structure which includes a first object, a second object and a thermal transfer adhesive material which is placed between the first object and the second object so as to be in contact with at least one of the first object or the second object. The heat transfer adhesive material includes a resin and at least one thermal conductive material, and the at least one thermal conductive material is distributed by being dispersed in the resin and forms surface contact with at least one of the first object or the second object.

Abstract: Disclosed are a single crystal wire and other single crystal articles, and a manufacturing method thereof. The method comprises the steps of: placing into a growth crucible at least one metal selected from the group consisting of gold, copper, silver, aluminum and nickel; heating and melting the metal placed in the growth crucible; growing a single crystal using metal crystal as a seed by Czochralski or Bridgman method; cutting the grown single crystal by electric discharge machining; and machining the cut single crystal and producing a wire or other articles such as a ring. In the method, the grown metal single crystal is cut into a disc-shaped piece by electric discharge machining. The piece is transformed into a single crystal wire or other articles by wire-cut electric discharge machining, and the single crystal wire can be used as a ring, a pendant, or a wire for high-quality cables for audio and video systems.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract: A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract: A stacked semiconductor device including a plurality of semiconductor chips stacked vertically, a plurality of scribe lane elements each forming a step with a semiconductor chip of the plurality of semiconductor chips and respectively formed on a side surface of each of the plurality of semiconductor chips, a redistribution element respectively formed on each of the plurality of semiconductor chips and the scribe lane elements, and a signal connection member formed on the side surface of each of the plurality of semiconductor chips and electrically connecting the redistribution elements.

Abstract: A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract: A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract: A flip chip package may include a semiconductor chip, a package substrate, a conductive magnetic bump and an anisotropic conductive member. The semiconductor chip may have a first pad. The package substrate may have a second pad confronting the first pad. The conductive magnetic bump may be interposed between the semiconductor chip and the package substrate to generate a magnetic force. The anisotropic conductive member may be arranged between the semiconductor chip and the package substrate. The anisotropic conductive member may have conductive magnetic particles induced toward the conductive magnetic bump by the magnetic force to electrically connect the first pad with the second pad. A predetermined number of the conductive magnetic particles may be positioned between the conductive magnetic bump and the pad, so that an electrical connection reliability between the pads may be increased.

Abstract: Provided is a tunable diffraction grating apparatus including: a diffraction grating portion having a diffraction grating with an linearly variable grating interval, the diffraction grating being formed of an elastic member; a drive portion connected to the diffraction grating portion and applying a force to the diffraction grating portion to vary the grating interval; and a controller for controlling the drive portion to adjust the grating interval depending on a specific wavelength input from the exterior. Therefore, the tunable diffraction grating apparatus can vary a grating interval of a diffraction grating using an elastic material so that a signal of a frequency bandwidth of THz can also be used. In addition, it is possible to simplify structure of the apparatus to reduce the manufacturing cost thereof.

Abstract: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

Abstract: Exemplary embodiments of the selective laser repair apparatus and method may allow the repair of metal bumps in a semiconductor device stack by applying a laser beam to a damaged and/or defective bump. Metal bumps may be repaired and individual chips and/or packages forming a device stack need not be separated. The operation of a control unit and a driving unit may position a laser unit such that a laser beam may be irradiated at the damaged and/or defective metal bump. An X-ray inspection unit may obtain information about the damaged and/or defective metal bump.

Abstract: Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

Abstract: Disclosed are a single crystal wire and a manufacturing method thereof. The method comprises the steps of: placing into a growth crucible at least one metal selected from the group consisting of gold, copper, silver, aluminum and nickel; heating and melting the metal placed in the growth crucible; growing a single crystal using the metal crystal as a seed by the Czochralski or Bridgman method; cutting the grown single crystal by electric discharge machining; and forming the cut single crystal into a wire. In the method, the grown metal single crystal is formed into a disc-shaped piece by electric discharge machining. The piece is formed into a single crystal wire by wire-cut electric discharge machining, and the single crystal wire can be used as a ring, a pendant or a wire within a high-quality cable making a connection in audio and video systems. Also, the single crystal formed into the disc-shaped piece by electric discharge machining can be used as a substrate and a target for deposition.

Abstract: A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a second UBM layer may be formed on the first photoresist pattern. A second photoresist pattern may be formed that exposes the first UBM layer. A solder bump may be formed in the opening. The second photoresist pattern and the first photoresist pattern may be removed using a stripper, thereby removing the second UBM layer by a lift-off method.

Abstract: A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.