Abstract: A method manufactures a gas sensor integrated on a semiconductor substrate. The method includes: realizing a first plurality of openings in the semiconductor substrate; realizing a crystalline silicon membrane suspended on the semiconductor substrate, forming an insulating cavity buried in the substrate; realizing a second plurality of openings in the semiconductor substrate, so as to totally suspend on the semiconductor substrate the crystalline silicon membrane; realizing, through a thermal oxidation process of the totally suspended crystalline silicon membrane, a suspended dielectric membrane; realizing, through selective photolithography, a heating element; realizing, through selective photolithography, electrodes and a pair of electric contacts; and selectively realizing, above the electrodes, a sensitive element by compacting layers of metallic oxide through a sintering process generated in the gas sensor by connecting the electrodes to a voltage generator.

Abstract: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.

Abstract: A method for manufacturing integrated capacitive elements on a semiconductor substrate includes depositing a first metallization layer on a first dielectric layer. The first metallization layer includes a lower plate for a capacitive element and an interconnection pad. The method further includes forming a second dielectric layer over the first dielectric layer, forming a first opening aligned with the lower plate through the second dielectric layer, and depositing a third dielectric layer on the second dielectric layer and the lower plate and covering sidewalls of the first opening. A second opening is formed through the third dielectric layer and aligned with the interconnection pad. A fourth dielectric layer is deposited on the whole wafer surface, wherein the fourth dielectric layer is etchable in a completely selective manner relative to the third dielectric layer.

Abstract: Described in the disclosure is a method for fabricating high-capacitance capacitive elements that are integrated in a semiconductor substrate. First a dielectric layer is formed over the surface of the substrate and a metal layer is deposited thereon. The metal layer is patterned and etched to form lower plates of the capacitive elements, as well as to form interconnection pads. Then, an intermediate dielectric layer is deposited on the lower plates and interconnection pads, and over the entire exposed surface of the substrate. Following that, a sacrificial conductive layer is deposited onto the intermediate dielectric layer, and the upper plates of the capacitive elements are formed out of the sacrificial conductive layer. Then, an upper dielectric layer is formed over the entire semiconductor, and openings are formed in this layer for the upper plates and the interconnection pads.

Abstract: A process for manufacturing a ferroelectric capacitor includes the steps of forming a first plate of a noble metal, preferably platinum, above an insulating layer of a wafer; forming a dielectric material layer with ferroelectric properties; and forming a second plate of a noble metal above said dielectric material layer. The first plate and the second plate are formed by electrochemical deposition of a metal.