Patents by Inventor Sehat Sutardja

Sehat Sutardja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and arrangements relating to semiconductor packages including multi-memory dies
    Patent number: 9117790
    Abstract: In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: August 25, 2015
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Method of fabricating a packaged semiconductor
    Patent number: 9117815
    Abstract: A method of fabricating a packaged semiconductor includes forming a conductive frame as an integral piece of conductive material. The frame includes an inner portion and a ring portion encircling the inner portion. The ring portion includes a first ring portion encircling first and second sides of the inner portion, and a first bar portion located on a third side of the inner portion. The method includes mounting a semiconductor die to a first surface of the inner portion of the frame. The die is configured to receive power via the first ring portion. The method includes applying a casing, which covers the die, to the frame. The method includes, after the casing is applied to the frame, removing (i) sections of the frame that connect the inner portion to the ring portion, and (ii) sections of the frame that connect the first ring portion to the first bar portion.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: August 25, 2015
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Multiport memory architecture
    Patent number: 9105319
    Abstract: The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 11, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Winston Lee, Sehat Sutardja, Donald Pannell
  • Methods and arrangements relating to semiconductor packages including multi-memory dies
    Patent number: 9105610
    Abstract: Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: August 11, 2015
    Assignee: Marvell World Trade Ltd
    Inventor: Sehat Sutardja
  • HIGH-BANDWIDTH DRAM USING INTERPOSER AND STACKING
    Publication number: 20150221614
    Abstract: Embodiments of the present disclosure provide a packaging arrangement that comprises an interposer and a system on chip (SoC) die disposed on the interposer. The packaging arrangement also comprises a plurality of memory dies stacked on one another to provide a stack of memory dies. A bottom memory die of the stack of memory dies is disposed on the substrate adjacent to the SoC die. Each memory die includes input/output (I/O) pads, wherein the I/O pads of a corresponding memory die are located on only one side of the corresponding memory die. The plurality of memory dies is stacked on one another such that all of the I/O pads are arranged along a same side of the stack of memory dies. The plurality of memory dies is also stacked such that all the I/O pads are exposed.
    Type: Application
    Filed: February 5, 2015
    Publication date: August 6, 2015
    Inventor: Sehat Sutardja
  • PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE
    Publication number: 20150221577
    Abstract: Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 3, 2015
    Publication date: August 6, 2015
    Inventors: Shiann-Ming Liou, Sehat Sutardja, Albert Wu, Chuan-Cheng Cheng, Chien-Chuan Wei
  • Apparatuses for bleeding current from a transformer of a solid-state light emitting diode
    Patent number: 9101018
    Abstract: A system configured to provide current to power a solid-state light emitting diode in accordance with a dimming level, wherein the dimming level corresponds to an amount of light provided from the solid-state light emitting diode. The system includes a transformer and a switch. The transformer includes a coil. The transformer is configured to receive a first current. The coil is configured to, based on the first current, output a second current to power the solid-state light emitting diode. The switch is configured to, based on a dimming level that corresponds to the amount of light provided from the solid-state light emitting diode of the system, bleed a portion of the second current out of the coil to a ground reference in order to divert the portion of the second current from being supplied to the solid-state light emitting diode.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 4, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Pantas Sutardja, Wanfeng Zhang, Jinho Choi
  • Class AB amplifiers
    Patent number: 9099969
    Abstract: An amplifier including first, second, third, and fourth switches, each having first and second terminals. The first terminal of each switch communicates with a respective load. The second terminal of the first switch communicates with the second terminal of the second switch. The second terminal of the third switch communicates with the second terminal of the fourth switch. A first terminal of a first capacitance communicates with the second terminals of the first and second switches. A first terminal of a second capacitance communicates with the second terminals of the third and fourth switches. A first inductance communicates with second terminals of the first and second capacitances.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: August 4, 2015
    Assignee: Marvell World Trade LTD.
    Inventors: Sehat Sutardja, Farbod Aram
  • Structures embedded within core material and methods of manufacturing thereof
    Patent number: 9087835
    Abstract: Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: July 21, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Albert Wu, Scott Wu
  • BALLAST RESISTOR FOR SUPER-HIGH-VOLTAGE DEVICES
    Publication number: 20150187754
    Abstract: An integrated circuit including a well region, a plurality of semiconductor regions implanted in the well region, and a plurality of polysilicon regions arranged on each of the plurality of semiconductor regions. The well region has a first doping level. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. The polysilicon regions are respectively connected directly to the plurality of semiconductor regions.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 2, 2015
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy, Siew Yong Chui
  • Semiconductor package assembly
    Patent number: 9059160
    Abstract: Embodiments of the present disclosure provide an apparatus comprising a substrate having (i) a first side configured to receive a semiconductor die and (ii) a second side disposed opposite to the first side. The substrate comprises a printed circuit board material. The apparatus further comprises an interposer that is (i) disposed in the substrate and (ii) configured to electrically couple the first side of the substrate and the second side of the substrate. The interposer comprises a semiconductor material.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: June 16, 2015
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • IMPULSE-ASSISTED LC TANK OSCILLATOR
    Publication number: 20150162873
    Abstract: An impulse generation circuit for a voltage controlled oscillator includes a zero-crossing detector configured to detect a zero-crossing time of an output signal of the voltage controlled oscillator. The zero-crossing time corresponds to a time that the output signal crosses from a first polarity to a second polarity. A delay circuit is configured to wait for a delay period based on the zero-crossing time and a voltage peak of the output signal. An impulse generation module is configured to generate an impulse subsequent to the delay period. An energy injector is configured to, in response to the impulse, connect a supply voltage to the output signal of the voltage controlled oscillator for a duration of the impulse.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 11, 2015
    Inventor: Sehat Sutardja
  • Current balancing circuits for light-emitting-diode-based illumination systems
    Patent number: 9055647
    Abstract: A system includes first, second, and third sets of LEDs and a control module. The first set of LEDs outputs light having wavelengths in a wavelength range in a spectrum of ultraviolet light and is coated with a phosphor to convert the ultraviolet light to blue light having wavelengths in a wavelength range in a spectrum of blue light. The second and third sets of LEDs output light having wavelengths in a wavelength range in the spectrum of blue light and is coated with phosphors to convert the blue light to light having wavelengths in a wavelength range in a spectrum of green, yellow, and red light. The second set of LEDs generates less red light than green light. The third set of LEDs generates less green light than red light. The current control module controls currents through the first, second, and third sets of LEDs to generate white light.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: June 9, 2015
    Assignee: Marvell World Trade LTD.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
  • WIRELESS HDD WITH INTEGRATED STORAGE CONTROLLER AND WIRELESS PROCESSING
    Publication number: 20150153954
    Abstract: A storage device includes a wireless interface and a processor. The wireless interface is configured to receive wireless data from a device external to the storage device. The wireless data includes at least one data packet configured according to a wireless communication protocol. The processor is configured to receive the wireless data including the at least one data packet from the wireless interface, generate a storage device data package including the wireless data, store, in a storage region of the storage device, the storage device data package including the wireless data, retrieve the storage device data package from the storage region, recover the wireless data from the storage device data package, and provide the wireless data to the wireless interface for transmission to the device external to the storage device.
    Type: Application
    Filed: June 4, 2013
    Publication date: June 4, 2015
    Inventors: Sehat Sutardja, Son Hong Ho
  • POWER/GROUND LAYOUT FOR CHIPS
    Publication number: 20150155202
    Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
    Type: Application
    Filed: February 3, 2015
    Publication date: June 4, 2015
    Inventors: Sehat Sutardja, Chung Chyung Han, Weidan Li, Shuhua Yu, Chuan-Cheng Cheng, Albert Wu
  • GPS-based traffic monitoring system
    Patent number: 9047765
    Abstract: A traffic information system for a vehicle comprises a transmitter and a global positioning system (GPS) associated with the vehicle that selectively generates location and vector data. A control module receives the location and vector data and wirelessly transmits the location and vector data using the transmitter when the vehicle is traveling on a first set of predetermined roads and does not transmit the location and vector data when the vehicle is traveling on a second set of predetermined roads.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: June 2, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Sehat Sutardja
  • Systems and methods for operating a power amplifier
    Patent number: 9048793
    Abstract: A power amplifier configured to receive an AC input signal and output, based on the AC input signal, an output voltage via a first output voltage terminal and a second output voltage terminal. The power amplifier includes a first transistor and a second transistor connected in a push-pull configuration, a first inductor, a second inductor, and a first capacitor. The first output voltage terminal is located between the first inductor and the first transistor. The second output voltage terminal is located between the second transistor and ground. The first capacitor is configured to provide a first circuit path between the first output voltage terminal and the second output voltage terminal. The first circuit path functions as a short circuit for even harmonics of a fundamental frequency of the AC input signal but does not function as a short circuit for the fundamental frequency of the AC input signal.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: June 2, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Poh Boon Leong, Ping Song, Sehat Sutardja
  • Power amplifier with feedback impedance for stable output
    Patent number: 9041467
    Abstract: An amplifier circuit amplifies a signal for wireless transmission. A feedback circuit, including a capacitor, is coupled to the amplifier circuit. Components of the feedback circuit are selected based on a feedback factor such that an input impedance to the amplifier circuit has a same impedance characteristic as a feedback circuit impedance of the feedback circuit.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Kan Li, Poh Boon Leong
  • INDUCTOR/TRANSFORMER OUTSIDE OF SILICON WAFER
    Publication number: 20150137342
    Abstract: An integrated circuit package includes an integrated circuit and an interposer layer. The interposer layer is arranged above the integrated circuit and includes an inductor formed at least partially within the interposer layer. The inductor includes a first pair of conductive pillars including a first conductive pillar and a second conductive pillar formed within a first via and a second via, respectively. The first via and the second via are formed through the interposer layer. The inductor further includes a first conductive trace connected across first ends of the first conductive pillar and the second conductive pillar on a first surface of the interposer layer, and a first conductive interconnect structure connected between second ends of the first conductive pillar and the second conductive pillar and the integrated circuit.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Inventor: Sehat Sutardja
  • FINAL LEVEL CACHE SYSTEM AND CORRESPONDING METHODS
    Publication number: 20150113214
    Abstract: A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Inventor: Sehat Sutardja