Abstract: A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address.

Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.

Abstract: A system including a packaging substrate and first and second integrated circuits arranged on the packaging substrate. The first integrated circuit includes a dynamic random access memory. The second integrated circuit includes a system-on-chip, which includes a hard disk controller to control a hard disk drive, a solid-state disk controller to control flash memory arranged external to the packaging substrate, and a dynamic random access memory controller to communicate with the dynamic random access memory. The hard disk controller and the solid-state disk controller access the dynamic random access memory via the dynamic random access memory controller. The dynamic random access memory controller is connected to the dynamic random access memory via the packaging substrate.

Abstract: A power amplifier configured to boost an AC signal. The power amplifier includes a first transistor, a second transistor, a first inductor connected between the first transistor and a voltage source, and a second inductor connected between the second transistor and ground. A first phase conditioner arranged at an input of the first transistor is configured to condition a phase of the AC signal such that the AC signal as received by the first transistor is out of phase with respect to the AC signal as received by the first inductor. A second phase conditioner arranged at an input of the second transistor is configured to condition a phase of the AC signal such that the AC signal as received by the second transistor is out of phase with respect to the AC signal as received by the second inductor.

Abstract: Embodiments of the present disclosure provide an apparatus that comprises a connection circuit situated within a substrate and configured to communicatively couple a first integrated circuit disposed adjacent to a top surface of the apparatus to a second integrated circuit disposed adjacent to a bottom surface of the apparatus. The apparatus further comprises one or more enclosed heat dissipation structures situated within the substrate and configured to convey heat away from the first and second integrated circuits.

Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.

Abstract: An integrated circuit package including a first substrate, a first die, a second die, a second substrate, and a system on chip. The first substrate includes a first portion including first connections, a second portion including no connections, a third portion including second connections, a first opening between the first portion and the second portion, and a second opening between the second portion and the third portion. The first die is arranged on the first substrate. The first die includes third connections to connect to the first connections via the first opening. The second die is arranged adjacent to the first die on the first substrate. The second die includes fourth connections to connect to the second connections via the second opening. The second substrate is connected to the first substrate. The system on chip is arranged on the second substrate between the first substrate and the second substrate.

Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).

Abstract: A metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit including first opposing side walls, second opposing side walls, a cavity with first and second openings, and openings in the first opposing side walls. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. The inner conducting structure is arranged in the cavity of the outer conducting structure and includes a body, and conducting extensions that extend from the body through the openings in the first opposing side walls. Oxide is arranged between the outer conducting structure and the inner conducting structure.

Abstract: A switching regulator includes a high-side driver configured to receive an input voltage, and a low-side driver configured to receive the input voltage. The high-side driver and the low-side driver are configured to provide an output voltage based on the input voltage. A charge pump module is configured to receive a supply voltage that varies between a first voltage level and a second voltage level greater than the first voltage level, generate the input voltage based on the supply voltage, and maintain the input voltage at the second voltage level independent of variations in the supply voltage.

Abstract: A system including a base portion, which includes first and second sets of light emitting diodes (LEDs) to emit blue light having first and second wavelengths in first and second wavelength ranges in a spectrum of blue light, a glass layer arranged at a second predetermined distance from the base portion, and a plurality of coatings of first and second phosphors having a predetermined length arranged in an alternating pattern on a surface of the glass layer facing toward the LEDs. The LEDs of the first and second sets are arranged on the base portion in an alternating pattern and are separated from each other by a first predetermined distance. Centers of the coatings of the first and second phosphors respectively align with centers of corresponding LEDs in the first and second sets.

Abstract: Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Abstract: A lamp including a first set of light emitting diodes configured to generate first light, a second set of light emitting diodes configured to generate second light, and a third set of light emitting diodes configured to generate third light. The first light, the second light, and the third light combine to produce white light. A first switch is located at a base portion of the lamp. The state of the first switch corresponds to a color temperature of the white light. A color temperature adjustment module is configured to vary outputs of the first, second, and third sets of light emitting diodes in accordance with the color temperature of the white light selected by a user using the first switch.

Abstract: A circuit including an amplifier. The circuit includes N capacitances that include first ends and second ends. The first ends communicate with an input of the amplifier. A first switch is configured to selectively connect the input of the amplifier to a reference potential during a first phase. N switches are configured to connect each of the second ends of the N capacitances to a voltage input, the reference potential and a voltage reference and selectively connect each of the second ends of the N capacitances to one of a voltage input, the reference potential and a voltage reference during a second phase. The first and second phases are non-overlapping.

Abstract: A system including a plurality of switches and a comparator. The plurality of switches is configured to respectively supply a plurality of currents via respective terminals to a plurality of sets of light emitting diodes. The sets of light emitting diodes are configured to respectively output light having wavelengths in a plurality of wavelength ranges in a spectrum of blue light. The comparator is configured to compare a reference voltage to a voltage at one of the terminals of one of the plurality of switches connected to one of the sets of light emitting diodes, and to adjust, based on the comparison, biasing of the plurality of switches to maintain a predetermined ratio of the plurality of currents.

Abstract: Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate.

Abstract: A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.

Abstract: A system including a plurality of cells connected in series in a rechargeable battery pack and a plurality of cell balancing modules. Each cell balancing module performs voltage balancing of a respective pair of cells. Each cell balancing module includes a communication module to (i) transmit, via a communication link, information about voltages of the respective pair of cells to an adjacent cell balancing module and (ii) receive, via the communication link, from the adjacent cell balancing module, information about voltages of cells corresponding to the adjacent cell balancing module. Each cell balancing module performs, based on the information received from the adjacent cell balancing module, the voltage balancing in response to a voltage difference between any of the plurality of cells being greater than or equal to a predetermined threshold instead of performing the voltage balancing based on a difference between voltages of the respective pair of cells.

Abstract: Aspects of the disclosure provide a circuit that includes a first circuit, a second circuit and a bridge circuit. The first circuit is coupled to a magnetic component to receive electric energy transferred via the magnetic component and thus configured to store the electric energy and generate a supply voltage. The second circuit is also coupled to the magnetic component. The second circuit is switchable and is configured to deplete a portion of the electric energy when the second circuit is switched on. The bridge circuit is coupled between the first circuit and the second circuit to provide a charge flow path when the second circuit is switched off.