Patents by Inventor Seiichiro Kanno
Seiichiro Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6677167Abstract: A wafer processing apparatus comprising a wafer stage, wherein a semiconductor wafer is mounted on the wafer stage so as to process the semiconductor wafer, wherein a holding mechanism of the wafer stage is commonly used for a plurality of wafer stages, and accordingly, the wafer stage can be changed into a wafer stage having a different function so as to process the semiconductor wafer.Type: GrantFiled: March 4, 2002Date of Patent: January 13, 2004Assignee: Hitachi High-Technologies CorporationInventors: Seiichiro Kanno, Hironobu Kawahara, Mitsuru Suehiro, Saburou Kanai, Toshio Masuda
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Patent number: 6646233Abstract: A wafer stage for use in wafer processing apparatus which comprises a liquid cooling jacket with a built-in coolant liquid circulation path and a ceramic plate that is attached onto the liquid cooling jacket and has therein a heater and an electrode for electrostatic chuck use, the wafer stage performing wafer processing while letting a wafer be mounted on the ceramic plate, wherein the liquid cooling jacket permits attachment of the ceramic plate through a coolant gas circulating gap as formed over the liquid cooling jacket while disposing between the liquid cooling jacket and the ceramic plate more than one heat resistant seal material containing therein an elastic body for sealing the coolant gas.Type: GrantFiled: March 5, 2002Date of Patent: November 11, 2003Assignee: Hitachi High-Technologies CorporationInventors: Seiichiro Kanno, Ken Yoshioka, Ryoji Nishio, Saburou Kanai, Hideki Kihara, Koji Okuda
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Publication number: 20030192864Abstract: ABSTRACT A plasma processing apparatus having a process chamber to process specimens; a status detecting unit for detecting the internal processing status of the process chamber and outputting a plurality of signals; and a signal converting unit for extracting an arbitrary number of signal processing filters from a signal filter database using a signal filter selector and creating an arbitrary number of device status signals. The signal converting unit creates fewer effective device status signals of a time series from the output signals.Type: ApplicationFiled: May 14, 2003Publication date: October 16, 2003Inventors: Junichi Tanaka, Hiroyuki Kitsunai, Ryoji Nishio, Seiichiro Kanno, Hideyuki Yamamoto
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Publication number: 20030168439Abstract: A wafer stage for use in wafer processing apparatus which comprises a liquid cooling jacket with a built-in coolant liquid circulation path and a ceramic plate that is attached onto the liquid cooling jacket and has therein a heater and an electrode for electrostatic chuck use, the wafer stage performing wafer processing while letting a wafer be mounted on the ceramic plate, wherein the liquid cooling jacket permits attachment of the ceramic plate through a coolant gas circulating gap as formed over the liquid cooling jacket while disposing between the liquid cooling jacket and the ceramic plate more than one heat resistant seal material containing therein an elastic body for sealing the coolant gas.Type: ApplicationFiled: March 5, 2002Publication date: September 11, 2003Inventors: Seiichiro Kanno, Ken Yoshioka, Ryoji Nishio, Saburou Kanai, Hideki Kihara, Koji Okuda
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Publication number: 20030164226Abstract: A wafer processing apparatus comprising a wafer stage, wherein a semiconductor wafer is mounted on the wafer stage so as to process the semiconductor wafer, wherein a holding mechanism of the wafer stage is commonly used for a plurality of wafer stages, and accordingly, the wafer stage can be changed into a wafer stage having a different function so as to process the semiconductor wafer.Type: ApplicationFiled: March 4, 2002Publication date: September 4, 2003Inventors: Seiichiro Kanno, Hironobu Kawahara, Mitsuru Suehiro, Saburou Kanai, Toshio Masuda
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Patent number: 6590179Abstract: A plasma processing apparatus having a process chamber to process specimens, a status detecting means for detecting the internal processing status of said process chamber and outputting a plurality of signals, and signal converting means for extracting an arbitrary number of signal processing filters from a signal filter database using a signal filter selecting means and creating an arbitrary number of device status signals. The signal converting means creates fewer effective device status signals of a time series from said output signals.Type: GrantFiled: February 26, 2001Date of Patent: July 8, 2003Assignee: Hitachi, Ltd.Inventors: Junichi Tanaka, Hiroyuki Kitsunai, Ryoji Nishio, Seiichiro Kanno, Hideyuki Yamamoto
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Patent number: 6583979Abstract: The present invention allows the electrostatically attracting electrode, whose size corresponds to large diameter wafers, to be fabricated easily and with precision. The first electrode is provided with a recess in which to install the second electrode. An insulating film is formed in the recess and then the second electrode is securely fitted in the recess. The assembled electrode is machined to make the surfaces of the first and second electrodes flush with each other in the same plane. The flat surfaces are covered with the sprayed electrostatic attraction film, which is the polished until it has a predetermined thickness. This fabrication process allows the electrostatic attraction electrode suitable to large-diameter wafers.Type: GrantFiled: July 6, 1998Date of Patent: June 24, 2003Assignee: Hitachi, Ltd.Inventors: Kazue Takahasi, Youichi Itou, Saburo Kanai, Seiichiro Kanno
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Patent number: 6549393Abstract: A wafer stage 2 for holding a semiconductor wafer in a plasma treatment apparatus by setting the wafer on the wafer stage, said wafer stage 2 comprising a base material 26 equipped with refrigerant flow paths for allowing a refrigerant for temperature adjustment to flow; a stress-reducing member 28 provided on the wafer setting side of said base material 26 and having a smaller thermal expansion coefficient than does said base material; a dielectric film 30 provided on the wafer setting side of said stress-reducing member; and a deflection-preventing member 29 provided on the wafer non-setting side of said base material and having a smaller thermal expansion coefficient than does said base material. When the wafer stage is used, the temperature of the wafer as a substrate to be processed can be controlled uniformly and very accurately.Type: GrantFiled: September 6, 2001Date of Patent: April 15, 2003Assignee: Hitachi, Ltd.Inventors: Seiichiro Kanno, Hironobu Kawahara, Mitsuru Suehiro, Saburo Kanai, Ken Yoshioka
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Publication number: 20030029572Abstract: A wafer stage 2 for holding a semiconductor wafer in a plasma treatment apparatus by setting the wafer on the wafer stage, said wafer stage 2 comprising a base material 26 equipped with refrigerant flow paths for allowing a refrigerant for temperature adjustment to flow; a stress-reducing member 28 provided on the wafer setting side of said base material 26 and having a smaller thermal expansion coefficient than does said base material; a dielectric film 30 provided on the wafer setting side of said stress-reducing member; and a deflection-preventing member 29 provided on the wafer non-setting side of said base material and having a smaller thermal expansion coefficient than does said base material. When the wafer stage is used, the temperature of the wafer as a substrate to be processed can be controlled uniformly and very accurately.Type: ApplicationFiled: April 1, 2002Publication date: February 13, 2003Inventors: Seiichiro Kanno, Hironobu Kawahara, Mitsuru Suehiro, Saburo Kanai, Ken Yoshioka
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Publication number: 20030030960Abstract: A wafer stage 2 for holding a semiconductor wafer in a plasma treatment apparatus by setting the wafer on the wafer stage, said wafer stage 2 comprising a base material 26 equipped with refrigerant flow paths for allowing a refrigerant for temperature adjustment to flow; a stress-reducing member 28 provided on the wafer setting side of said base material 26 and having a smaller thermal expansion coefficient than does said base material; a dielectric film 30 provided on the wafer setting side of said stress-reducing member; and a deflection-preventing member 29 provided on the wafer non-setting side of said base material and having a smaller thermal expansion coefficient than does said base material. When the wafer stage is used, the temperature of the wafer as a substrate to be processed can be controlled uniformly and very accurately.Type: ApplicationFiled: September 6, 2001Publication date: February 13, 2003Inventors: Seiichiro Kanno, Hironobu Kawahara, Mitsuru Suehiro, Saburo Kanai, Ken Yoshioka
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Publication number: 20020114123Abstract: A plasma processing apparatus comprises: a body that comprises a vacuum processing chamber with a wafer stage on which a semiconductor wafer is held, a plasma producing unit for producing plasma within the vacuum chamber, and a high frequency source for applying a high frequency bias voltage to the wafer stage. A control unit controls various parameters of the body of the plasma processing apparatus. The control unit comprises a detecting unit for detecting the high frequency voltage or high frequency current applied to the wafer stage and for calculating a difference in phase between the high frequency voltage and the high frequency current, and a unit for obtaining a characteristic of the plasma or an electric characteristic of the plasma processing apparatus based on the detected high frequency voltage, the detected high frequency current, and the obtained difference in phase.Type: ApplicationFiled: March 2, 2001Publication date: August 22, 2002Inventors: Ryoji Nishio, Seiichiro Kanno, Hideyuki Yamamoto, Akira Kagoshima
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Publication number: 20020104832Abstract: A plasma processing apparatus having a process chamber to process specimens, further comprising a status detecting means for detecting the internal processing status of said process chamber and outputting a plurality of signals and signal converting means for extracting an arbitrary number of signal processing filters from a signal filter database by a signal filter selecting means and creating arbitrary number of device status signals; wherein said signal converting means create a fewer effective device status signals of a time series from said output signals.Type: ApplicationFiled: February 26, 2001Publication date: August 8, 2002Inventors: Junichi Tanaka, Hiroyuki Kitsunai, Ryoji Nishio, Seiichiro Kanno, Hideyuki Yamamoto
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Patent number: 6373681Abstract: A sample processing method includes electrostatically attracting and holding a sample on an electrostatic chuck which includes a pair of electrodes having different polarities and being concentrically disposed, and a dielectric film formed on top surfaces of the pair of electrodes, by applying a DC voltage between the pair of electrodes. The sample which is attracted and held on the chuck through the dielectric film is subjected to plasma processing while applying a bias voltage. The application of the bias voltage applied during plasma processing is stopped after termination of processing the sample, and an unbalance between electric charges stored on attracting portions of the dielectric film formed on the electrodes is eliminated by continuing generation of the plasma for a specific time after stopping the application of the bias voltage. The plasma is extinguished after an elapse of the specific time.Type: GrantFiled: April 13, 2001Date of Patent: April 16, 2002Assignee: Hitachi, Ltd.Inventors: Seiichiro Kanno, Tatehito Usui, Ken Yoshioka, Saburo Kanai, Youichi Itou
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Patent number: 6370007Abstract: An electrostatic chuck for holding a substrate, including an electrode block which serves as an electrode for electrostatic attraction and a plurality of electrostatic attraction arranged on a surface of the electrode block. The electrostatic attraction members are disposed so as to attract the substrate electrostatically and to come in contact with the substrate. An insulating material covers the surface of the electrode block other than attraction surfaces of the electrostatic attraction members. Grooves made by the insulating material are provided between the individual electrostatic attraction members.Type: GrantFiled: March 1, 2001Date of Patent: April 9, 2002Assignee: Hitachi, Ltd.Inventors: Kazue Takahasi, Youichi Itou, Saburo Kanai, Seiichiro Kanno
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Publication number: 20010025691Abstract: A semiconductor manufacturing apparatus includes a unit for generating a plasma in a vacuum chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum chamber, a high frequency power supply for applying a high frequency voltage to the wafer stage, a wafer voltage probe for measuring a voltage of the semiconductor wafer at a rear surface of the semiconductor wafer, a current and voltage probe for measuring at least one of a voltage and a current applied to the wafer stage from the high frequency power supply, and a control portion. The control portion obtains an impedance from the semiconductor wafer to earth through the plasma on the basis of a voltage value of the semiconductor wafer measured by the wafer voltage probe, and a voltage value or a current value measured by the current and voltage probe, and performs a processing based on the obtained impedance.Type: ApplicationFiled: March 7, 2001Publication date: October 4, 2001Inventors: Seiichiro Kanno, Ryoji Nishio, Tsutomu Tetsuka, Junichi Tanaka, Hideyuki Yamamoto, Kazuyuki Ikenaga, Saburou Kanai
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Publication number: 20010019472Abstract: A sample processing method includes electrostatically attracting and holding a sample on an electrostatic chuck which includes a pair of electrodes having different polarities and being concentrically disposed, and a dielectric film formed on top surfaces of the pair of electrodes, by applying a DC voltage between the pair of electrodes. The sample which is attracted and held on the chuck through the dielectric film is subjected to plasma processing while applying a bias voltage. The application of the bias voltage applied during plasma processing is stopped after termination of processing the sample, and an unbalance between electric charges stored on attracting portions of the dielectric film formed on the electrodes is eliminated by continuing generation of the plasma for a specific time after stopping the application of the bias voltage. The plasma is extinguished after an elapse of the specific time.Type: ApplicationFiled: April 13, 2001Publication date: September 6, 2001Inventors: Seiichiro Kanno, Tatehito Usui, Ken Yoshioka, Saburo Kanai, Youichi Itou
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Publication number: 20010009497Abstract: An electrostatic chuck for holding a substrate, including an electrode block which serves as an electrode for electrostatic attraction and a plurality of electrostatic attraction arranged on a surface of the electrode block. The electrostatic attraction members are disposed so as to attract the substrate electrostatically and to come in contact with the substrate. An insulating material covers the surface of the electrode block other than attraction surfaces of the electrostatic attraction members. Grooves made by the insulating material are provided between the individual electrostatic attraction members.Type: ApplicationFiled: March 1, 2001Publication date: July 26, 2001Inventors: Kazue Takahasi, Youichi Itou, Saburo Kanai, Seiichiro Kanno
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Patent number: 6243251Abstract: An electrostatic chuck includes a pair of electrodes having different polarities, and a dielectric film, formed on top surfaces of the pair of electrodes, on which a sample to be electrostatically attracted and held when a DC voltage is applied between the pair of electrodes, wherein the respective amounts of electric charges stored on attracting portions of the dielectric film corresponding to the pair of electrodes, directly before stopping supply of the DC voltage applied between the pair of electrodes, are substantially equal to each other. With this chuck, the electric charges stored on the attracting portions of the dielectric film after stopping supply of the DC voltage can be eliminated due to the balance between the electric charges having different polarities. The electrostatic chuck is subjected to a significantly reduced residual attracting force.Type: GrantFiled: August 25, 1999Date of Patent: June 5, 2001Assignee: Hitachi, Ltd.Inventors: Seiichiro Kanno, Tatehito Usui, Ken Yoshioka, Saburo Kanai, Youichi Itou
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Patent number: 5946184Abstract: An electrostatic chuck includes a pair of electrodes having different polarities; and a dielectric film, formed on top surfaces of the pair of electrodes, on which a sample is to be electrostatically attracted and held when a DC voltage is applied between the pair of electrodes; wherein the respective amounts of electric charges stored on attracting portions of the dielectric film corresponding to the pair of electrodes, directly before stopping supply of the DC voltage applied between the pair of electrodes, are substantially equal to each other. With this chuck, the electric charges stored on the attracting portions of the dielectric film after stopping supply of the DC voltage can be eliminated due to the balance between the electric charges having different polarities. The electrostatic chuck is subjected to a significantly reduced residual attracting force.Type: GrantFiled: September 11, 1997Date of Patent: August 31, 1999Assignee: Hitachi, Ltd.Inventors: Seiichiro Kanno, Tatehito Usui, Ken Yoshioka, Saburo Kanai, Youichi Itou
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Patent number: 5781400Abstract: The present invention allows the electrostatically attracting electrode, whose size corresponds to large-diameter wafers, to be fabricated easily and with precision.The first electrode 1 is provided with a recess in which to install the second electrode 2. An insulating film 4 is formed in the recess and then the second electrode is securely fitted in the recess. The assembled electrode is machined to make the surfaces of the first and second electrodes flush with each other in the same plane. The flat surfaces are covered with the sprayed electrostatic attraction film 3, which is then polished until it has a predetermined thickness. This fabrication process allows the electrostatic attraction electrode suitable to large-diameter wafers.Type: GrantFiled: September 18, 1996Date of Patent: July 14, 1998Assignee: Hitachi, Ltd.Inventors: Kazue Takahashi, Youichi Itou, Saburo Kanai, Seiichiro Kanno