Patents by Inventor Seong Jun Jang
Seong Jun Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128502Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.Type: ApplicationFiled: August 14, 2023Publication date: April 18, 2024Inventors: Sa Heum Kim, Yong Jun Jang, Yong Gu Kim, Sung Man Cho, Sun Ho Choi, Seong Hyeon Choi, Kyu Sung Park, Young Gyoon Ryu, Suk Gi Hong, Pil Sang Yun, Myeong Ju Ha, Hyun Beom Kim, Hwi Chul Yang
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Publication number: 20240120616Abstract: A secondary battery includes an electrode assembly having a positive electrode provided with a positive electrode tab, a separator, and a negative electrode provided with a negative electrode tab, the positive electrode, the separator, and the negative electrode being wound, the electrode assembly having a core part at a center thereof; a can configured to receive the electrode assembly therein, the negative electrode tab being connected to the can; a cap assembly coupled to an opening of the can, the positive electrode tab being connected to the cap assembly; and a reinforcing member provided on an end of the separator exposed beyond the positive electrode or the negative electrode to prevent heat of the positive electrode tab or the negative electrode tab from being transferred to the separator.Type: ApplicationFiled: April 19, 2022Publication date: April 11, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Soon Kwan KWON, Su Taek JUNG, Seok Hoon JANG, Hyeok JEONG, Sang Ho BAE, Byeong Kyu LEE, Seong Won CHOI, Min Wook KIM, Yong Jun LEE
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Publication number: 20240097119Abstract: A method of manufacturing a composite electrode for an all-solid-state battery includes: preparing a precursor solution by mixing at least one solid electrolyte precursor and at least one polar solvent; stirring the precursor solution; preparing an electrode slurry by adding an active material to the stirred precursor solution; and heat-treating the electrode slurry and obtaining the composite electrode for the all-solid-state battery, wherein the composite electrode for the all-solid-state battery includes: the active material; and a coating layer disposed on the active material and including a solid electrolyte.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicants: HYUNDAI MOTOR COMPANY, Kia CorporationInventors: Sun Ho CHOI, Yong Jun JANG, In Woo SONG, Sang Heon LEE, Sang Soo LEE, So Young KIM, Seong Hyeon CHOI, Sa Heum KIM, Jae Min LIM
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Patent number: 11714762Abstract: An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a first arbiter circuit and a second arbiter circuit. The first arbiter circuit receives a normal access request signal and a refresh access request signal and generates a first output signal in response to a logical operation to arbitrate between the normal access reqeuest signal and the refresh access request signal. The second arbiter circuit configured to receive the first output signal and a delayed signal of the first output signal, and to generate a second output signal in response to a logical operation of the first output signal and the delayed signal. The second output signal has a first logical state indicative of granting the read or write access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.Type: GrantFiled: August 1, 2022Date of Patent: August 1, 2023Assignee: Integrated Silicon Solution, (Cayman) Inc.Inventors: Geun-Young Park, Seong-Jun Jang
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Publication number: 20220365888Abstract: An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a first arbiter circuit and a second arbiter circuit. The first arbiter circuit receives a normal access request signal and a refresh access request signal and generates a first output signal in response to a logical operation to arbitrate between the normal access reqeuest signal and the refresh access request signal. The second arbiter circuit configured to receive the first output signal and a delayed signal of the first output signal, and to generate a second output signal in response to a logical operation of the first output signal and the delayed signal. The second output signal has a first logical state indicative of granting the read or write access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.Type: ApplicationFiled: August 1, 2022Publication date: November 17, 2022Inventors: Geun-Young Park, Seong-Jun Jang
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Patent number: 11442875Abstract: An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a set-reset latch circuit receiving a normal access request signal and a refresh access request signal as first and second input signals and generating a first output signal having zero or more signal transitions in response to the order the first input signal and the second input signal is asserted. The arbitration control circuit further includes a unidirectional delay circuit applying a unidirectional delay to the first output signal and a D-flip-flop circuit latching the first output signal as data in response to the delayed signal as clock. The D-flip-flop generates a second output signal having a first logical state indicative of granting the normal access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.Type: GrantFiled: May 18, 2020Date of Patent: September 13, 2022Assignee: Integrated Silicon Solution, (Cayman) Inc.Inventors: Geun-Young Park, Seong-Jun Jang
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Patent number: 11328771Abstract: A sense amplifier circuit implements a sense scheme using sense amplifier feedback control to disconnect the bit lines from the sense circuit during the read operation after the bit line signals are sensed. In this manner, read disturbance during the read operation is prevented. In some embodiments, the sense amplifier circuit includes a pair of pass gates to couple a pair of differential bit lines to a sense circuit. The sense amplifier circuit further includes a feedback control circuit to open the pair of pass gates in response to at least one of the sensed signals at the sense circuit changing logical state. The pair of pass gates are opened to disconnect the pair of differential bit lines from the sense circuit.Type: GrantFiled: January 6, 2021Date of Patent: May 10, 2022Assignee: Integrated Silicon Solution, (Cayman) Inc.Inventor: Seong-Jun Jang
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Publication number: 20220084590Abstract: A sense amplifier circuit implements a sense scheme using sense amplifier feedback control to disconnect the bit lines from the sense circuit during the read operation after the bit line signals are sensed. In this manner, read disturbance during the read operation is prevented. In some embodiments, the sense amplifier circuit includes a pair of pass gates to couple a pair of differential bit lines to a sense circuit. The sense amplifier circuit further includes a feedback control circuit to open the pair of pass gates in response to at least one of the sensed signals at the sense circuit changing logical state. The pair of pass gates are opened to disconnect the pair of differential bit lines from the sense circuit.Type: ApplicationFiled: January 6, 2021Publication date: March 17, 2022Inventor: Seong-Jun Jang
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Publication number: 20210357335Abstract: An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a set-reset latch circuit receiving a normal access request signal and a refresh access request signal as first and second input signals and generating a first output signal having zero or more signal transitions in response to the order the first input signal and the second input signal is asserted. The arbitration control circuit further includes a unidirectional delay circuit applying a unidirectional delay to the first output signal and a D-flip-flop circuit latching the first output signal as data in response to the delayed signal as clock. The D-flip-flop generates a second output signal having a first logical state indicative of granting the normal access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.Type: ApplicationFiled: May 18, 2020Publication date: November 18, 2021Inventors: Geun-Young Park, Seong-Jun Jang
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Patent number: 10331575Abstract: A memory device incorporates a chip enable protection circuit implementing a secured chip enable method providing a passcode protected enable scheme with secure chip disable for the memory device. The passcode can be programmed at manufacturing or programmed by the user. Memory device access is enabled by receiving the correct passcode and memory device access is denied when the wrong passcode is entered. Furthermore, the secured chip enable method implements secure chip disable where the memory device is disabled in response to receiving wrong passcodes repeatedly for a maximum number of tries.Type: GrantFiled: April 11, 2017Date of Patent: June 25, 2019Assignee: Integrated Silicon Solution, Inc.Inventor: Seong Jun Jang
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Publication number: 20180293181Abstract: A memory device incorporates a chip enable protection circuit implementing a secured chip enable method providing a passcode protected enable scheme with secure chip disable for the memory device. The passcode can be programmed at manufacturing or programmed by the user. Memory device access is enabled by receiving the correct passcode and memory device access is denied when the wrong passcode is entered. Furthermore, the secured chip enable method implements secure chip disable where the memory device is disabled in response to receiving wrong passcodes repeatedly for a maximum number of tries.Type: ApplicationFiled: April 11, 2017Publication date: October 11, 2018Inventor: Seong Jun Jang
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Patent number: 9496030Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.Type: GrantFiled: May 24, 2016Date of Patent: November 15, 2016Assignee: Integrated Silicon Solution, Inc.Inventors: Justin Kim, Geun-Young Park, Seong Jun Jang
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Publication number: 20160284401Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.Type: ApplicationFiled: May 24, 2016Publication date: September 29, 2016Inventors: Justin Kim, Geun-Young Park, Seong Jun Jang
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Patent number: 9373393Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.Type: GrantFiled: June 5, 2014Date of Patent: June 21, 2016Assignee: Integrated Silicon Solution, Inc.Inventors: Justin Kim, Geun-Young Park, Seong Jun Jang
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Patent number: 9324426Abstract: A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.Type: GrantFiled: June 2, 2014Date of Patent: April 26, 2016Assignee: Integrated Silicon Solution, Inc.Inventors: Seong Jun Jang, Justin Kim, Geun-Young Park
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Patent number: 9319038Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.Type: GrantFiled: October 20, 2014Date of Patent: April 19, 2016Assignee: Integrated Silicon Solution, Inc.Inventor: Seong Jun Jang
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Publication number: 20150357035Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.Type: ApplicationFiled: June 5, 2014Publication date: December 10, 2015Inventors: Justin Kim, Geun-Young Park, Seong Jun Jang
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Publication number: 20150357036Abstract: A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.Type: ApplicationFiled: June 5, 2014Publication date: December 10, 2015Inventors: Geun-Young Park, Seong Jun Jang, Justin Kim
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Publication number: 20150348624Abstract: A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.Type: ApplicationFiled: June 2, 2014Publication date: December 3, 2015Applicant: Integrated Silicon Solution, Inc.Inventors: Seong Jun Jang, Justin Kim, Geun-Young Park
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Patent number: 9202561Abstract: A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.Type: GrantFiled: June 5, 2014Date of Patent: December 1, 2015Assignee: Integrated Silicon Solution, Inc.Inventors: Geun-Young Park, Seong Jun Jang, Justin Kim