Abstract: The address transition detecting circuit includes two identical address transition detecting signal generating module, an inverter and a signal combining module. Both of the two address transition detecting signal generating modules have a unilateral delay circuit for generating an output pulse at the rising edge of the address signal and an output pulse at the falling edge of the address signal. The address transition detecting signal generating module can control the width of the two output pulses by controlling the delay times of the corresponding unilateral delay circuit. The signal combining module outputs the ATD signal having pulses at both the rising edge and falling edge of the address signal. The present application uses two unilateral delay circuits to control the width of the ATD signal at the rising edge and the falling edge of the address signal, thereby significantly preventing the width of the ATD signal from influence of the burr on the address line.

Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Abstract: Disclosed is a synchronous memory device with a dual sensing output path having two data paths, each of which has a latch circuit and a sense amplifier. The synchronous memory device includes a first data reading means for amplifying and latching the data from memory cells in response to odd clock signals, a second data reading means coupled in parallel to the first data reading means for amplifying and latching the data from memory cells in response to the even clock signals, and a clock signal generating means for alternatively generating even clock signals and odd clock signals. According the second data reading means outputs to an output buffer the latched data therein while the second data reading means amplifies the data. As a result, the synchronous memory device according to the present invention may reduces the cycle time to read the cell data by up to 33%.

Abstract: The present invention discloses a synchronous memory device capable of processing data at a high speed in a read path of the memory device, by decreasing the timing margin of the external clock signal which is input into the input registers, of the pipeline structure the memory device comprises: a) an address pad receiving an address signal; b) a first input register coupled to the address pad, wherein the first input registers including:, 1) a first switching device coupled to the address pad, wherein the first switching device is controlled by a first control signal; 2) a first latch device for storing the address signal from the first switching device; and 3) a second switching device coupled to the first latch device, wherein the second switching device is controlled by a second control signal, and wherein-the second control signal is 180.degree.