Abstract: A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.

Abstract: A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first conductive interconnect. Over the first interlevel dielectric layer and the first conductive interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first conductive interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

Abstract: One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array.

Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.

Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.

Abstract: An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad.

Abstract: A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.

Abstract: A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second MTJ device having a second physical configuration. The first access latency is less than the second access latency.

Abstract: An integrated magnetic film enhanced inductor and a method of forming an integrated magnetic film enhanced inductor are disclosed. The integrated magnetic film enhanced inductor includes an inductor metal having a first portion and a second portion, a top metal or bottom metal coupled to the inductor metal, and an isolation film disposed one of in, on, and adjacent to at least one of the first portion and the second portion of the inductor metal. The isolation film includes a magnetic material, such as a magnetic film.

Abstract: An entropy source and a random number (RN) generator are disclosed. In one aspect, a low-energy entropy source includes a magneto-resistive (MR) element and a sensing circuit. The MR element is applied a static current and has a variable resistance determined based on magnetization of the MR element. The sensing circuit senses the resistance of the MR element and provides random values based on the sensed resistance of the MR element. In another aspect, a RN generator includes an entropy source and a post-processing module. The entropy source includes at least one MR element and provides first random values based on the at least one MR element. The post-processing module receives and processes the first random values (e.g., based on a cryptographic hash function, an error detection code, a stream cipher algorithm, etc.) and provides second random values having improved randomness characteristics.

Abstract: A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue.

Abstract: A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

Abstract: In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) structure including a conductive layer on a substrate. The method also includes depositing a sacrificial layer on the conductive layer before depositing a patterning film layer.

Abstract: Embodiments of the disclosure are directed to generating a random number. An embodiment of the disclosure passes a current from a read operation through a magnetic tunnel junction (MTJ) to cause a first magnetization orientation of a free layer to switch to a second magnetization orientation, the switch in magnetization orientation causing a change in a resistance of the MTJ, and periodically samples the resistance of the MTJ to generate a bit value for the random number.

Abstract: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage.

Abstract: A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

Abstract: A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a pre-programmed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metal-insulator-metal (MIM) capacitor structure.

Abstract: A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.

Abstract: A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures.

Abstract: A system and method to initiate a housekeeping operation at a mobile device is disclosed. In a particular embodiment, a method at a mobile device includes modifying a scheduled housekeeping operation in response to determining that the mobile device is in a charging mode.