Patents by Inventor Seung H. Kang

Seung H. Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LOW COST PROGRAMMABLE MULTI-STATE DEVICE
    Publication number: 20140063895
    Abstract: A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a pre-programmed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metal-insulator-metal (MIM) capacitor structure.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang
  • MULTI-LEVEL MEMORY CELL USING MULTIPLE MAGNETIC TUNNEL JUNCTIONS WITH VARYING MGO THICKNESS
    Publication number: 20140050019
    Abstract: A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Kangho Lee, Taehyun Kim, Jung Pill Kim, Seung H. Kang
  • MTP MTJ DEVICE
    Publication number: 20140048894
    Abstract: Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Xia Li, Kangho Lee, Jung Pill Kim, Taehyun Kim, Wah Nam Hsu, Seung H. Kang, Xiaochun Zhu, Wei-Chuan Chen, Sungryul Kim
  • MONOLITHIC MULTI-CHANNEL ADAPTABLE STT-MRAM
    Publication number: 20140043890
    Abstract: A monolithic multi-channel resistive memory includes at least one first bank associated with a first channel and tuned according to first device attributes and/or first circuit attributes. The memory also includes at least one second bank associated with a second channel and tuned according to second device attributes and/or second circuit attributes.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Seung H. Kang, Xiaochun Zhu
  • TUNABLE MULTI-TIERED STT-MRAM CACHE FOR MULTI-CORE PROCESSORS
    Publication number: 20140047184
    Abstract: A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Seung H. Kang, Xiaochun Zhu, Xiaoxia Wu
  • Fabrication and integration of devices with top and bottom electrodes including magnetic tunnel junctions
    Patent number: 8644063
    Abstract: An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: February 4, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang
  • AMORPHOUS ALLOY SPACER FOR PERPENDICULAR MTJs
    Publication number: 20140027869
    Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.
    Type: Application
    Filed: February 19, 2013
    Publication date: January 30, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Kangho Lee, Wei-Chuan Chen, Seung H. Kang
  • Resistance based memory having two-diode access device
    Patent number: 8638590
    Abstract: A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: January 28, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Wuyang Hao, Jungwon Suh, Kangho Lee, Tae Hyun Kim, Jung Pill Kim, Seung H. Kang
  • STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION
    Publication number: 20140015080
    Abstract: A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device.
    Type: Application
    Filed: September 25, 2013
    Publication date: January 16, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Seung H. Kang, Xia Li, Shiqun Gu, Kangho Lee, Xiaochun Zhu
  • REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY (STT-MRAM)
    Publication number: 20140015077
    Abstract: A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Kangho Lee, Seung H. Kang, Xiaochun Zhu
  • CONTACT SUPPORT PILLAR STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE
    Publication number: 20140015127
    Abstract: In one aspect, there is provided a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and has a contact support pillar opening formed therein. Contact support pillars that comprise a conductive metal and have a metal extension are located within the opening of the passivation layer.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 16, 2014
    Inventors: Mark A. Bachman, Donald S. Bitting, Sailesh Chittipeddi, Seung H. Kang, Sailesh M. Merchant
  • NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION
    Publication number: 20140010006
    Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.
    Type: Application
    Filed: September 10, 2013
    Publication date: January 9, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Hari M. Rao, Jung Pill Kim, Seung H. Kang, Xiaochun Zhu, Taehyun Kim, Kangho Lee, Xia Li, Wah Nam Hsu, Wuyang Hao, Jungwon Suh, Nicholas K. Yu, Matthew M. Nowak, Steven M. Millendorf, Asaf Ashkenazi
  • Method and apparatus of probabilistic programming multi-level memory in cluster states of bi-stable elements
    Patent number: 8625337
    Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: January 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Wenqing Wu, Kendrick H. Yuen, Xiaochun Zhu, Seung H. Kang, Matthew Michael Nowak, Jeffrey A. Levin, Robert Gilmore, Nicholas Yu
  • Asymmetric write scheme for magnetic bit cell elements
    Patent number: 8625338
    Abstract: Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: January 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaochun Zhu, Hari M. Rao, Jung Pill Kim, Seung H. Kang
  • Magnetic random access memory (MRAM)layout with uniform pattern
    Patent number: 8614912
    Abstract: A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: December 24, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Taehyun Kim, Xia Li, Jung Pill Kim, Seung H. Kang
  • Self-body biasing sensing circuit for resistance-based memories
    Patent number: 8611132
    Abstract: A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: December 17, 2013
    Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Seong-Ook Jung, Jisu Kim, Youngdon Jung, Jung Pill Kim, Seung H. Kang
  • ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS
    Publication number: 20130314980
    Abstract: A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.
    Type: Application
    Filed: July 30, 2013
    Publication date: November 28, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Jung Pill Kim, Taehyun Kim, Seung H. Kang
  • Programmable logic sensing in magnetic random access memory
    Patent number: 8593173
    Abstract: A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: November 26, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Pill Kim, Tae Hyun Kim, Wenqing Wu, Xiaochun Zhu, Seung H. Kang
  • Symmetrically switchable spin-transfer-torque magnetoresistive device
    Patent number: 8592929
    Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device includes magnetic tunnel junctions (MTJs) with reduced switching current asymmetry. At least one switching asymmetry balance layer (SABL) near the free layer of the MTJ reduces a first switching current Ic(p-ap) causing the value of the first switching current to be nearly equal to the value of a second switching current Ic(ap-p) without increasing the average switching current of the device. The SABL may be a non-magnetic switching asymmetry balance layer (NM-SABL) and/or a magnetic switching asymmetry balance layer (M-SABL).
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: November 26, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Wei-Chuan Chen, Kangho Lee, Xiaochun Zhu, Seung H. Kang
  • Non-volatile memory array configurable for high performance and high density
    Patent number: 8587982
    Abstract: Embodiments include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 19, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Pill Kim, Hari M. Rao, Xiaochun Zhu, Xia Li, Seung H. Kang