Abstract: A first semiconductor device includes an interfacial layer over a substrate, a first high-? dielectric layer over the interfacial layer, a second high-? dielectric layer over the first high-? dielectric layer, a Ti—Si mixing layer over the second high-? dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-? dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-? dielectric layer, a second high-? dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-? dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-? dielectric layer over the interfacial layer, forming a second high-? dielectric layer over the first high-? dielectric layer, and forming a gate electrode layer over the second high-? dielectric layer.

Abstract: A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

Abstract: Embodiments of the invention are directed to a semiconductor device that includes a channel fin; a trench adjacent to an upper region of the channel fin; and an oxygen-blocking layer within the trench. The oxygen-blocking layer includes an oxygen gettering material configured to remove oxygen from an environment to which the oxygen-blocking layer is exposed.

Abstract: Example fluid collection devices, and related systems and methods of use are described. The fluid collection device includes a fluid impermeable barrier having a rear region and a front region at least partially defining an opening and positioned on the fluid impermeable barrier to be at least proximate to a urethra of a user. The fluid impermeable barrier at least partially defines a chamber and an aperture sized and dimensioned to receive a conduit therethrough. The fluid collection device includes a fluid permeable body positioned at least partially within the chamber to extend across at least a portion of the opening and configured to wick fluid away from the opening. The fluid collection device includes a dry adhesive region positioned on the rear region of the fluid impermeable barrier at least partially distal to the opening to interface a garment worn by the user.

Abstract: VFET devices having a porous bottom air spacer formed by oxidation are provided. In one aspect, a VFET device includes: at least one fin present on a substrate, wherein the at least one fin serves as a vertical fin channel of the VFET device; a bottom source/drain region at a base of the at least one fin; a bottom air-containing spacer disposed on the bottom source/drain region; a gate stack alongside the at least one fin; a top spacer above the gate stack at a top of the at least one fin; and a top source/drain region at a top of the at least one fin. A method of forming a VFET device is also provided.

Abstract: A first semiconductor device includes an interfacial layer over a substrate, a first high-? dielectric layer over the interfacial layer, a second high-? dielectric layer over the first high-? dielectric layer, a Ti—Si mixing layer over the second high-? dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-? dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-? dielectric layer, a second high-? dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-? dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-? dielectric layer over the interfacial layer, forming a second high-? dielectric layer over the first high-? dielectric layer, and forming a gate electrode layer over the second high-? dielectric layer.

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

Abstract: Embodiments of the invention are directed to a semiconductor device that includes a channel fin; a trench adjacent to an upper region of the channel fin; and an oxygen-blocking layer within the trench. The oxygen-blocking layer includes an oxygen gettering material configured to remove oxygen from an environment to which the oxygen-blocking layer is exposed.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a top spacer trench adjacent to an upper region of the channel fin. An oxygen-blocking layer is deposited within the top spacer trench and over the upper region of the channel fin. A top spacer is formed within the top spacer trench and over a portion of the oxygen-blocking layer that is within the top spacer trench. The oxygen-blocking layer includes an oxygen gettering material.

Abstract: Embodiments disclosed herein include fluid collection assemblies with at least one securement body. In an embodiment, a fluid collection assembly is disclosed. The fluid collection assembly includes a fluid impermeable barrier at least defining a chamber, at least one opening, and a fluid outlet. The fluid collection assembly also includes at least one porous material disposed in the chamber and at least one securement body configured to limit movement of the fluid collection assembly relative to a region about a urethral opening of a patient. The at least one securement body includes at least one of a plurality of fibers exhibiting an average lateral dimension of about 5 ?m or less, a plurality of suction cups, or at least one friction material exhibiting a coefficient of static friction that is greater than at least a portion of the at least one porous material.

Abstract: A case for a catheter system is disclosed, the case including a case body including a first side coupled to a second side. The case can include padding with a plurality of cavities to receive components of the catheter system and a strap to secure components of the catheter system to an interior of the case body. The case can further include one or more clips affixed to an interior wall of the first side or the second side of the case body. The one or more clips can be configured to secure additional catheter tubing or an external catheter to the interior wall of case body.

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a top spacer trench adjacent to an upper region of the channel fin. An oxygen-blocking layer is deposited within the top spacer trench and over the upper region of the channel fin. A top spacer is formed within the top spacer trench and over a portion of the oxygen-blocking layer that is within the top spacer trench. The oxygen-blocking layer includes an oxygen gettering material.

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

Abstract: A method of cleaning a low-k spacer cavity by a low energy RF plasma at a specific substrate temperature for a defect free epitaxial growth of Si, SiGe, Ge, III-V and III-N and the resulting device are provided. Embodiments include providing a substrate with a low-k spacer cavity; cleaning the low-k spacer cavity with a low energy RF plasma at a substrate temperature between room temperature to 600° C.; and forming an epitaxy film or a RSD in the low-k spacer cavity subsequent to the low energy RF plasma cleaning.

Abstract: A integrated circuit including an n-doped high-k dielectric layer conformally within a first opening in a dielectric layer such that the n-doped high-k dielectric layer is in direct contact with a portion of a substrate exposed at a bottom of the first opening, a p-doped high-k dielectric layer conformally within a second opening in the dielectric layer such that the p-doped high-k dielectric layer is in direct contact with a portion of the substrate exposed at a bottom of the second opening, a shared work function metal conformally within the first opening and the second opening above and in direct contact with both the p-doped high-k dielectric layer and the n-doped high-k dielectric layer, and a bulk fill material above and in direct contact with the shared work function metal.