Patents by Inventor Shahab Siddiqui
Shahab Siddiqui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9252232Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.Type: GrantFiled: March 6, 2015Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
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Publication number: 20160027893Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Unoh Kwon, Wing L. Lai, Vijay Narayanan, Sean M. Polvino, Ravikumar Ramachandran, Shahab Siddiqui
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Publication number: 20160003980Abstract: A method is provided for manufacturing ophthalmically-acceptable, distortion-free silicone hydrogel contact lenses without the use of volatile organic solvents in the manufacturing process. The contact lenses are extract with an extraction liquid comprising an aqueous solution of a non-volatile organic solvent, such as ethyl lactate.Type: ApplicationFiled: March 14, 2014Publication date: January 7, 2016Applicant: CooperVision International Holding Company, LPInventors: Yuwen Liu, AKM Shahab Siddiqui, Yuan Ji, Junhao Ge
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Patent number: 9224826Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.Type: GrantFiled: February 12, 2014Date of Patent: December 29, 2015Assignee: International Business Machines CorporationInventors: Unoh Kwon, Wing L. Lai, Vijay Narayanan, Sean M. Polvino, Ravikumar Ramachandran, Shahab Siddiqui
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Patent number: 9224740Abstract: A method of deep trench isolation which includes: forming a semiconductor on insulator (SOI) substrate comprising a bulk semiconductor substrate, a buried insulator layer and a semiconductor layer on the buried insulator layer (SOI layer), one portion of the SOI substrate having a dynamic random access memory buried in the bulk semiconductor substrate (eDRAM) and a deep trench fin contacting the eDRAM and a second portion of the SOI substrate having an SOI fin in contact with the buried insulator layer; conformally depositing sequential layers of oxide, high-k dielectric material and sacrificial oxide on the deep trench fin and the SOI fin; stripping the sacrificial oxide over the SOI fin to expose the high-k dielectric material over the SOI fin; stripping the exposed high-k dielectric material over the SOI fin to expose the oxide layer over the SOI fin.Type: GrantFiled: December 11, 2014Date of Patent: December 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Sean M. Polvino, Shahab Siddiqui
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Patent number: 9196700Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.Type: GrantFiled: March 6, 2015Date of Patent: November 24, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
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Patent number: 9193118Abstract: Methods of manufacturing contact lenses using ophthalmic lens molds having a molding surface comprising a thermoplastic polymer, the molding surface having a percent polarity from 3% to 20% and a surface energy from about 25 mN/m to about 40 mN/m to cast mold a polymerizable composition having a surface tension from about 20 mN/m to about 25 mN/m, wherein a surface energy differential of the surface tension of the polymerizable composition less the surface energy of the molding surface less than or equal to zero (0); and silicone hydrogel contact lens bodies so manufactured are described.Type: GrantFiled: July 29, 2011Date of Patent: November 24, 2015Assignee: CooperVision International Holding Company, LPInventors: A. K. M. Shahab Siddiqui, David Robert Morsley, Sarah L. Almond, Richard C. Rogers, Ian Bruce, Lee Darren Norris, Edyta S. Bialek, Benjamin S. Sheader
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Patent number: 9177868Abstract: A method of manufacturing a semiconductor structure by forming an oxide layer above a substrate; optionally annealing the oxide layer to densify the oxide layer; forming a first sacrificial gate above the substrate; removing the first dummy gate; optionally annealing the first gate oxide layer; and forming a first replacement metal gate above the gate oxide layer. In some embodiments selective nitridation may be performed during the annealing step.Type: GrantFiled: March 28, 2014Date of Patent: November 3, 2015Assignee: International Business Machines CorporationInventors: Unoh Kwon, Wing L. Lai, Vijay Narayanan, Ravikumar Ramachandran, Shahab Siddiqui
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Patent number: 9156214Abstract: Ophthalmic lens molds made from one or more thermoplastic polymers with average polarities from about 1% to about 7%, ophthalmic lenses including silicone hydrogel contact lenses molded using these less polar thermoplastic polymers, and related methods are described. When the molds are used to cast mold silicone hydrogel contact lenses, the resulting polymerized lens bodies have ophthalmically acceptably wettable surfaces.Type: GrantFiled: July 8, 2011Date of Patent: October 13, 2015Assignee: CooperVision International Holding Company, LPInventors: Lee Darren Norris, Edyta S. Bialek, Sarah L. Almond, David Robert Morsley, A. K. M. Shahab Siddiqui, Richard C. Rogers, Ian Bruce, Benjamin S. Sheader
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Publication number: 20150279744Abstract: A method of manufacturing a semiconductor structure by forming an oxide layer above a substrate; optionally annealing the oxide layer to densify the oxide layer; forming a first sacrificial gate above the substrate; removing the first dummy gate; optionally annealing the first gate oxide layer; and forming a first replacement metal gate above the gate oxide layer. In some embodiments selective nitridation may be performed during the annealing step.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Unoh Kwon, Wing L. Lai, Vijay Narayanan, Ravikumar Ramachandran, Shahab Siddiqui
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Publication number: 20150255463Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.Type: ApplicationFiled: March 6, 2014Publication date: September 10, 2015Applicant: International Business Machines CorporationInventors: Takashi Ando, Balaji Kannan, Siddarth Krishnan, Unoh Kwon, Shahab Siddiqui
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Publication number: 20150235944Abstract: A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Ronald G. Filippi, Erdem Kaltalioglu, Shahab Siddiqui, Ping-Chuan Wang, Lijuan Zhang
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Publication number: 20150228747Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.Type: ApplicationFiled: February 12, 2014Publication date: August 13, 2015Applicant: International Business Machines CorporationInventors: Unoh Kwon, Wing L. Lai, Vijay Narayanan, Sean M. Polvino, Ravikumar Ramachandran, Shahab Siddiqui
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Patent number: 9099461Abstract: A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.Type: GrantFiled: June 7, 2012Date of Patent: August 4, 2015Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Min Dai, Jinping Liu, Paul A. Ronsheim, Joseph F. Shepard, Jr., Shahab Siddiqui
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Patent number: 9087722Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.Type: GrantFiled: November 14, 2014Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Charlotte D. Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
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Patent number: 9087784Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.Type: GrantFiled: January 29, 2014Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Carl J. Radens, Shahab Siddiqui
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Publication number: 20150187901Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.Type: ApplicationFiled: March 6, 2015Publication date: July 2, 2015Inventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
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Publication number: 20150179459Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than ?, which can be advantageously employed to reduce the leakage current through a gate dielectric.Type: ApplicationFiled: March 6, 2015Publication date: June 25, 2015Inventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
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Patent number: 9040369Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.Type: GrantFiled: January 29, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Shahab Siddiqui, Michael P. Chudzik, Carl J. Radens
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Patent number: 9029959Abstract: A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.Type: GrantFiled: June 29, 2012Date of Patent: May 12, 2015Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Michael P. Chudzik, Min Dai, Joseph F. Shepard, Jr., Shahab Siddiqui, Yanfeng Wang, Jinping Liu