Abstract: A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a voltage peak or amplitude of a first signal input and a second signal input (specifically, differential output of VCO). At a given time, only one small-size amplitude detection circuit is activated to load VCO, reducing the impact on LC resonant frequency. The plurality of small-size detection circuits work sequentially, and an automatic averaging of their outputs can significantly improve the peak detector fluctuation (caused by process variation and device mismatch) compared to each single small-size amplitude detection circuit.

Abstract: A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a voltage peak or amplitude of a first signal input and a second signal input (specifically, differential output of VCO). At a given time, only one small-size amplitude detection circuit is activated to load VCO, reducing the impact on LC resonant frequency. The plurality of small-size detection circuits work sequentially, and an automatic averaging of their outputs can significantly improve the peak detector fluctuation (caused by process variation and device mismatch) compared to each single small-size amplitude detection circuit.

Abstract: A domain control circuit includes a power regulator to supply power for a first domain on a power rail and a sequencing circuit to control the power regulator, and a clock gate signal to activate the domain. The sequencing circuit receives a domain control signal to control activation and deactivation of the domain. The domain control circuit deactivates the clock gate signal to the domain after controlling the power regulator to supply power for the domain on a power rail. In this manner, a voltage droop in a supply voltage on a power rail is reduced. In some examples, the clock gate signal to the domain is deactivated after a voltage increase on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit to determine a number of the parallel regulator circuits to be activated to power the domain.

Abstract: A digital signal processor includes analog to digital converters to convert an analog voltage to digital voltage in unit intervals of an analog signal. A decision feedback equalizer (DFE) determines a first level of a digital sum of a digital voltage in a first UI and digital voltages of adjacent UIs (taps). The DFE identifies predetermined sequences of levels of consecutive UIs that include the first level and selects one of the predetermined sequences to decode digital data encoded in the analog signal in the UI. The DSP may be programmable to include taps from UIs that may affect the first UI. The predetermined sequences may include levels of the digital sums of consecutive UIs of the analog signal. The predetermined sequences may be identified in a look-up table based on the first level.

Abstract: Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold.

Abstract: Techniques are disclosed for circuit configuration. Information is obtained on logical distances between reconfigurable fabric circuits on a semiconductor chip. A plurality of clusters is identified within the reconfigurable fabric circuits on the semiconductor chip. A cycle count separation across the plurality of cluster is evaluated using information on the logical distances. A plurality of counter initializations is calculated where the counter initializations compensate for the cycle count separation across the clusters. A plurality of counters is initialized, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, where the counters are distributed across the clusters, and where the initializing is based on the counter initializations that were calculated. The plurality of counters is started to coordinate configuration across the plurality of clusters.

Abstract: Disclosed embodiments select a proper hum frequency reference by utilizing one or more functional logic circuits within a cluster. The slowest logic circuit is determined, and an instance of that logic circuit is used in timing circuitry for the cluster. Multiple logic circuits with similar characteristics are incorporated into the timing circuit. Each cluster is interconnected to a second level timing circuit. Each cluster inputs timing information into the second level timing circuit. The second level timing circuit then determines when the next cycle, or tic, of the self-generated clock starts, and the process repeats, providing a self-generated clock signal.

Abstract: Techniques are disclosed for circuit synchronization. Information is obtained on logical distances between circuits on a semiconductor chip. A plurality of clusters is determined within the chip circuits, where a cluster within the plurality of clusters is synchronized to a tic cycle boundary. A tic cycle count separation is evaluated across the clusters using the information on the logical distances. A plurality of counter initializations is calculated where the counter initializations compensate for the tic cycle count separation across the clusters. A plurality of counters is initialized, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, where the counters are distributed across the clusters, and where the initializing is based on the counter initializations that were calculated. The plurality of counters is started to coordinate calculation across the plurality of clusters.

Abstract: Disclosed embodiments select a proper hum frequency reference by utilizing one or more functional logic circuits within a cluster. he slowest logic circuit is determined, and an instance of that logic circuit is used in timing circuitry for the cluster. Multiple logic circuits with similar characteristics are incorporated into the timing circuit. Each cluster is interconnected to a second level timing circuit. Each cluster inputs timing information into the second level timing circuit. The second level timing circuit then determines when the next cycle, or tic, of the self-generated clock starts, and the process repeats, providing a self-generated clock signal.

Abstract: A system, method, and apparatus for generating a low noise bias current to improve jitter performance in a wide frequency range LC-based phase-locked loop (PLL) circuit for multi-speed clocking applications. A plurality of noise-reducing stages are coupled in series and disposed between a power supply and a voltage controlled oscillator (VCO) including: a first stage VCO regulator; and a second stage bias circuit having a plurality of PMOS transistors cascode-coupled to each other and optionally grouped into one or more parallel branches of cascode-coupled transistor pairs. Each branch can be automatically enabled by a calibration code based on the desired reference clock signal in order to provide a wide range of currents to the voltage controlled oscillator. The cascode coupled pair includes a bias transistor coupled in series with a self-biased current buffer to provide high output impedance with minimal current change for any input voltage change from noise.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: ABSTRACT The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: A plurality of on-chip temperature sensors are selectively distributed across an integrated circuit. The temperature sensors generate signals indicative of operating temperatures experienced by the portions of the integrated circuit on which the temperature sensors are disposed. Based on the temperatures of the portions of the integrated circuit, operation of particular circuitry of the integrated circuit is dynamically adjusted to counteract the effects of undesirable or unexpected operating temperatures.

Abstract: A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.

Abstract: An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.