Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: An invention is disclosed for a process monitor based keeper scheme for dynamic circuits. A semiconductor die having a process monitor based keeper scheme of the embodiments of the present invention generally includes a plurality of dynamic circuits, each having an adaptive keeper circuit capable of being adjusted based on a bit code. In addition, a plurality of process monitors is included. Each process monitor is disposed within a corresponding die block, which defines a local area of the die. The process monitors are capable of detecting process corner data for the corresponding die block. In communication with each process monitor and the plurality of dynamic circuits is a test processor unit. The test processor unit obtains process corner data for each die block from the process monitor disposed within the die block, and provides a bit code based on the process corner data to the dynamic circuits disposed within the die block.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: A system and method of adjusting an I/O receiver includes providing an amplification control parameter to the I/O receiver. A temperature of the I/O receiver is monitored and the amplification control parameter to the I/O receiver is adjusted according to the temperature of the I/O receiver.

Abstract: A method and apparatus for adjusting clock skew involves sensing a temperature at a location on a microprocessor. A temperature sensor indicates a temperature value of the location on the microprocessor. The temperature value is monitored, and a tunable buffer is adjusted dependent on the monitoring. The tunable buffer is used to adjust clock skew. A memory is arranged to store an adjustment value for the tunable buffer.

Abstract: A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.

Abstract: A method and apparatus that dynamically control an amount of offset current generated by a keeper device are provided. Further, a method and apparatus that use a temperature-controlled keeper device to dynamically optimize an evaluation performance of a dynamic circuit are provided. In particular, when IC temperature is relatively high, i.e., there is increased current leakage in the dynamic circuit, an amount of offset current output by the temperature-controlled keeper may be increased, thereby preventing a dynamic node of the dynamic circuit from being discharged, or otherwise adversely affected, by the increased current leakage. Alternatively, when the IC temperature is relatively low, i.e., there is decreased current leakage in the dynamic circuit, the amount of offset current output by the temperature-controlled keeper may be decreased, thereby ensuring that the offset current is not so large that it severely degrades the evaluation performance.

Abstract: A method and apparatus that dynamically control an amount of offset current generated by a keeper device are provided. Further, a method and apparatus that use a temperature-controlled keeper device to dynamically optimize an evaluation performance of a dynamic circuit are provided. In particular, when IC temperature is relatively high, i.e., there is increased current leakage in the dynamic circuit, an amount of offset current output by the temperature-controlled keeper may be increased, thereby preventing a dynamic node of the dynamic circuit from being discharged, or otherwise adversely affected, by the increased current leakage. Alternatively, when the IC temperature is relatively low, i.e., there is decreased current leakage in the dynamic circuit, the amount of offset current output by the temperature-controlled keeper may be decreased, thereby ensuring that the offset current is not so large that it severely degrades the evaluation performance.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.

Abstract: An invention is disclosed for a process monitor based keeper scheme for dynamic circuits. A semiconductor die having a process monitor based keeper scheme of the embodiments of the present invention generally includes a plurality of dynamic circuits, each having an adaptive keeper circuit capable of being adjusted based on a bit code. In addition, a plurality of process monitors is included. Each process monitor is disposed within a corresponding die block, which defines a local area of the die. The process monitors are capable of detecting process corner data for the corresponding die block. In communication with each process monitor and the plurality of dynamic circuits is a test processor unit. The test processor unit obtains process corner data for each die block from the process monitor disposed within the die block, and provides a bit code based on the process corner data to the dynamic circuits disposed within the die block.

Abstract: A bit line that has a feedback path from the bit line to a storage cell on the bit line is provided. The feedback path allows the bit line to discharge through a discharge device that is connected to a non-discharging local bit line. Further, a discharge device capable of discharging a global bit line even when a storage cell connected to the discharge device is not being evaluated is provided. Further, a method to perform a memory array operation by discharging a bit line using multiple discharge devices is provided.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Abstract: A bit line that has a feedback path from the bit line to a storage cell on the bit line is provided. The feedback path allows the bit line to discharge through a discharge device that is connected to a non-discharging local bit line. Further, a discharge device capable of discharging a global bit line even when a storage cell connected to the discharge device is not being evaluated is provided. Further, a method to perform a memory array operation by discharging a bit line using multiple discharge devices is provided.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Abstract: An electronic circuit has a register connected to a sense amplifier via a bitline (the sense amplifier has a primary precharge circuit), and a secondary precharge circuit also connected to the bitline. For bitlines that are relatively long, the secondary precharge circuit is located at a distal end of the bitline with respect to the sense amplifier. The secondary precharge circuit initially pulls up the voltage of the bitline, and the primary precharge circuit in the sense amplifier completes the precharging of the bitline. The secondary precharge circuit includes a cascode transistor coupled to the bitline via a feedback circuit. The feedback circuit is enabled during the precharge phase, when the bitline is discharged below a preset threshold. The threshold of the secondary precharge circuit can be set such that any skew between the precharge pulses of the secondary precharge circuit and the sense amplifier does not affect the falling bitline during the sense amplifier evaluate phase.