Abstract: Disclosed are compounds for inhibiting lipoamide dehydrogenase (Lpd), and methods of treating tuberculosis.

Abstract: Disclosed by the present invention are an aqueous polyurethane functional mask substrate and an application thereof. Two kinds of water-based polyurethane dispersions are used as the main components of the mask substrate. The transdermal penetration and absorption of functional ingredients such as whitening, moisturizing and anti-aging ingredients in facial mask products are promoted by means of the special cross-linked structures of polyurethane films. During use, a mask is evenly applied to the face; and after the mask dries, the entire mask may be removed directly or removed after being moistened using water. The mask substrate according to the present invention is also applicable to body masks such as a hand mask, a neck mask and a back mask.

Abstract: Provided are transaminase mutants and uses thereof. The transaminase mutant is obtained by one or more amino acid mutations occurring in SEQ ID NO: 2 or is a mutant with a conserved amino acid mutation obtained by taking the sequence SEQ ID NO: 1 of a wild-type CvTA transaminase as a reference. Compared with wild-type transaminases, the catalytic activity of the mutant is improved to different degrees, so that the production efficiency of chiral amine compound synthesis may be improved.

Abstract: Disclosed is a method for determining 224Ra in a sediment by using a pulse ionization chamber emanometer, which belongs to the technical field of analysis and measurement. A pulse ionization chamber emanometer (PIC), a new emanometer, is used. Based on the half-life characteristics of different radon isotopes, one can separate the 220Rn activity from the total counts by dual counting. The resulting 220Rn measurement then can be used to determine the 224Ra activity in sediment according to the principle of secular radioactive equilibrium.

Abstract: A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.

Abstract: An apparatus comprises a toggle member, a plurality of pogo pins, and a test board in operable communication with the toggle member. The pogo pins are coupled to the toggle member to move along a first axis when the toggle member moves along the first axis. Each pogo pin includes a plunger that moves within the pogo pin along the first axis. The pogo pins and respective plungers contact a top surface of the DUT when the DUT is coupled to the test board and positioned so that a conductor on its outer surface is aligns to and contacts a conductive region of the test board. Movement of the toggle member along the first axis translates to the plungers, applying a pressure sufficient to the top surface of the DUT to ensure flushmount electrical contact between the conductor of the DUT and the conductive region.

Abstract: A memory device including a reference voltage (VREF) generator and method for operating the same to improve memory sensing margin, and extend operational temperature range and life of the device are disclosed. Generally, the device further includes an array of non-volatile memory cells divided into a plurality of blocks, a sensing circuit coupled to the array to receive and compare memory signals therefrom to the VREF to read data from the cells. The Local reference voltage generator is configured to provide one of a number of reference voltages to the sensing circuit based on which of the blocks is being read. The array can be divided based on row and column addresses of cells in the blocks. Where the cells include 1T1C ferroelectric random access memory (F-RAM) cells, and the reference voltages are selected based on a lowest P-term or highest U-term of the cells in the block being read.

Abstract: Polypeptides comprising a cell penetrating amino acid sequence and an interferon regulatory factor 5 (IRF5) targeting amino acid sequence are disclosed, where the IRF5 targeting amino acid sequence is one or more of RHATRHG (SEQ ID NO:1), KSRDFRL (SEQ ID NO:2) and GPRDMPP (SEQ ID NO:3), as well as methods of using these polypeptides to treat diseases, such as autoimmune and inflammatory diseases.

Abstract: A memory device including a reference voltage (VREF) generator and method for operating the same to improve memory sensing margin, and extend operational temperature range and life of the device are disclosed. Generally, the device further includes an array of non-volatile memory cells divided into a plurality of blocks, a sensing circuit coupled to the array to receive and compare memory signals therefrom to the VREF to read data from the cells. The Local reference voltage generator is configured to provide one of a number of reference voltages to the sensing circuit based on which of the blocks is being read. The array can be divided based on row and column addresses of cells in the blocks. Where the cells include 1T1C ferroelectric random access memory (F-RAM) cells, and the reference voltages are selected based on a lowest P-term or highest U-term of the cells in the block being read.

Abstract: The present disclosure provides a method for preventing and/or treating a stress-induced disease in a subject in need of such treatment, comprising administering to said subject an effective amount of tanshinone IIA or a derivative of tanshinone IIA, or a pharmaceutically acceptable salt, solvate, hydrate, isotopologue, or prodrug of tanshinone IIA or a derivative of tanshinone IIA, and optionally a pharmaceutically acceptable carrier or excipient.

Abstract: The present disclosure provides a soluble P-selectin (sP-sel) interfering the interaction between stem cells and niches to mobilize stem cells from bone marrow. The mobilization of stem cells with sP-sel can treat a subject in need of preservation, repair, or regeneration of a tissue, or revascularization.

Abstract: The invention creates engineered surface protein expression on vesicles for specific targeting and delivery of agents to autophagic and apoptotic cells. Moreover, the vesicles of the invention can achieve a synergistic effect on the targeting and drug delivery to autophagic and apoptotic cells and autophagic and apoptotic cells-containing tissues.

Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device with a reduced number of masking and etching steps is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate to expose a portion of the surface, and forming first spacers on sidewalls of the opening. A conductive layer is formed on the portion of the surface exposed in the opening and separated from the first spacers on the sidewalls of the opening by a gap therebetween. A bottom electrode of a ferroelectric capacitor is formed over the conductive layer and in the gap laterally of the conductive layer, a ferroelectric dielectric formed on the bottom electrode between the first spacers, and a top electrode formed on the ferroelectric dielectric.

Abstract: The invention creates engineered surface protein expression on vesicles for specific targeting and delivery of agents to autophagic and apoptotic cells. Moreover, the vesicles of the invention can achieve a synergistic effect on the targeting and drug delivery to autophagic and apoptotic cells and autophagic and apoptotic cells-containing tissues.

Abstract: A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL1), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL2), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL1, WL2, the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.

Abstract: Disclosed herein is an apparatus that includes a ferroelectric capacitor disposed on a damascene barrier film, and fabrication methods thereof. The damascene barrier film includes a hydrogen barrier region and an oxygen barrier region, with the oxygen barrier being in contact with a bottom surface of the ferroelectric capacitor. Other embodiments are also disclosed herein.

Abstract: A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL1), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL2), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL1, WL2, the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.

Abstract: Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric capacitor formed thereon.

Abstract: A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL1), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL2), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL1, WL2, the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.

Abstract: Disclosed herein is an apparatus that includes a ferrocapacitor disposed on a damascene barrier film. The damascene barrier film includes a hydrogen barrier region and an oxygen barrier region, with each being in contact with a bottom surface of the ferrocapacitor.