Abstract: A mounting apparatus for mounting a speaker to a computer case, includes a base plate assembled on the computer case, a fixing member configured to fix two corners on a top edge of the speaker, and an elastic sheet configured to fix a bottom edge of the speaker.

Abstract: A fan controlling circuit for detecting rotational speed of a fan, includes a comparison circuit and a controlling chipset. The comparison circuit receives a rotational speed signal from the fan at one input terminal, a reference voltage at another input terminal, and outputs a filtered rotational speed signal at an output terminal. The controlling chipset receives the filtered rotational speed signal, and outputs control signals to control the rotational speed of the fan.

Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

Abstract: A power facility has at least one power element and a system monitors/controls at least a portion of the power facility. In the system, a field drop is coupled to each element for monitoring same, reporting status data, receiving control information, and controlling such element. A local area network (LAN) couples each field drop to a hub, and a data server is coupled to the hub. The data server receives the status data from each field drop and takes any appropriate action necessary in response thereto, and also allows a user to access any particular field drop of the system to read data for the corresponding element and issue control commands for the element to be carried out by the corresponding field drop.

Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

Abstract: Consistent with an aspect of the present invention, a lateral bipolar transistor is provided that exhibits similar performance as that of high speed vertical bipolar junction transistors. The lateral bipolar transistor includes a polysilicon side-wall-spacer (PSWS) that forms a contact with the base of the transistor, and thus avoids the process step of aligning a contact mask to a relatively thin base region. The side wall spacer allows self-alignment of the base/emitter region, and has reduced base resistance and junction capacitance. Accordingly, improved cutoff frequency (f?) and maximum oscillation frequency (fmax) can be achieved. Moreover, this novel topology enables the realization of Bipolar CMOS (BiCMOS) technology on insulating substrates, such as SOI.

Abstract: The present invention provides a use of soluble P-selectin in treating systemic hemorrhagic conditions, stabilizing blood pressure, and protecting hypoxic/ischemic tissues. Also provided is a use of anthrax lethal toxin in treating thrombotic conditions.

Abstract: The present invention can improve and/or modify data retention lifetimes for ferroelectric devices by baking them prior to or during packaging. A ferroelectric device is programmed to a particular state and then baked for a selected period of time at a selected temperature. This pre-baking or imprinting causes the device to be imprinted or have a preference for the particular state and reduces loss of signal margin over time, thereby at least partially preserving data retention capabilities.

Abstract: The present invention can improve and/or modify data retention lifetimes for ferroelectric devices by baking them prior to or during packaging. A ferroelectric device is programmed to a particular state and then baked for a selected period of time at a selected temperature. This pre-baking or imprinting causes the device to be imprinted or have a preference for the particular state and reduces loss of signal margin over time, thereby at least partially preserving data retention capabilities.

Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.

Abstract: A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr(x)Ru(y)O3, on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500° C. to 700° C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr(x)Ru(y)O3. The second anneal is performed at 300° C. to 500° C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.

Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.

Abstract: A ferroelectric thin film capacitor and a method for producing the same wherein the capacitor dielectric includes multi-layered crystallographic textures. An integrated circuit device, such as a non-volatile memory device, includes at least one capacitor having a top and bottom electrode thereof and a ferroelectric dielectric layer therebetween. The ferroelectric dielectric layer comprises a first ferroelectric layer having a first crystallographic texture forming a main body of the dielectric layer and a second ferroelectric layer having a second differing crystallographic texture forming an interface layer between the main body and one of the top and bottom electrodes.

Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17/&mgr;m2 or less.

Abstract: A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.

Abstract: A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.

Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17/&mgr;m2 or less.

Abstract: A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr(x)Ru(y)O3, on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500° C. to 700° C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr(x)Ru(y)O3. The second anneal is performed at 300° C. to 500° C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.