Abstract: A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr(x)Ru(y)O3, on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500° C. to 700° C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr(x)Ru(y)O3. The second anneal is performed at 300° C. to 500° C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.

Abstract: A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.

Abstract: A method of patterning and etching an integrated circuit ferroelectric capacitor uses a layer of PZT which has the same composition as the capacitor PZT as a temporary encapsulation during PZT grain growth annealing. The temporary encapsulation PZT also serves as a hard mask to pattern the top electrode and the capacitor PZT layers for a capacitor-on-oxide structure, i.e., two-layer-one-step patterning. The process of the present invention can also be modified as a three-layer-one-step patterning process and can be applied to a capacitor-on-plug structure.

Abstract: The ferroelectric thin film is formed from a liquid composition by the sol-gel processing which has a large amount of polarization, remarkably improved retention and imprint characteristics as compared with a PZT, minute grains and fine film quality, homogeneous electrical properties, and low leakage currents and which is suited for nonvolatile memories. The ferroelectric thin film of the present invention comprising a metal oxide represented by the general formula: (PbV CaW SrX LaY)(ZrZ Ti1−Z)O3, wherein 0.9≦V≦1.3, 0≦W≦0.1, 0≦X≦0.1, 0<Y≦0.1, 0<Z≦0.

Abstract: Ferroelectric switching properties are severely degraded in a hydrogen ambient atmosphere. By controlling the polarity of the capacitors in a ferroelectric memory during the manufacturing process, the amount of degradation can be significantly reduced. After metalization of a ferroelectric memory wafer, all of the ferroelectric capacitors are poled in the same direction. The polarization vector is in a direction that helps to counteract hydrogen damage. A hydrogen gas anneal is subsequently performed to control underlying CMOS structures while maintaining ferroelectric electrical properties. The wafer is then passivated and tested.

Abstract: The ferroelectric thin film is formed from a liquid composition by the sol-gel processing which has a large amount of polarization, remarkably improved retention and imprint characteristics as compared with a PZT, minute grains and fine film quality, homogeneous electrical properties, and low leakage currents and which is suited for nonvolatile memories. The ferroelectric thin film of the present invention comprising a metal oxide represented by the general formula: (Pbv Caw SrX LaY)(ZrZ Ti1−Z)O3, wherein 0.9≦V≦1.3, 0≦W≦0.1, 0≦X≦0.1, 0<Y≦0.1, 0<Z≦0.