Patents by Inventor Shan Wang

Shan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949892
    Abstract: A method and apparatus for neural network based cross component prediction with low-bit precision during encoding or decoding of an image frame or a video sequence, which may include reconstructing a chroma component based on a received luma component using a pre-trained deep neural network (DNN) cross component prediction (CCP) model for chroma prediction, and updating a set of parameters of the pre-trained DNN CCP model with low-bit precision. The method may also include generating an updated DNN CCP model for chroma prediction with low-bit precision based on at least one video sequence, and using the updated DNN CCP model for cross component prediction of the at least one video sequence at reduced processing time.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 2, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Sheng Lin, Wei Jiang, Wei Wang, Shan Liu, Xiaozhong Xu
  • Patent number: 11948090
    Abstract: In the present disclosure, a method for compressing a feature map is provided, where the feature map is generated by passing a first input through a deep neural network (DNN). A respective optimal index order and a respective optimal unifying method are determined for each of super-blocks that are partitioned from the feature map. A selective structured unification (SSU) layer is subsequently determined based on the respective optimal index order and the respective optimal unifying method for each of the super-blocks. The SSU layer is added to the DNN to form an updated DNN, and is configured to perform unification operations on the feature map. Further, a first estimated output is determined, where the first estimated output is generated by passing the first input through the updated DNN.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: April 2, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Wei Jiang, Wei Wang, Shan Liu
  • Publication number: 20240107750
    Abstract: A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode, and the insulating layer extends above a top-most surface of the substrate.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Inventors: Chin-Shan WANG, Shun-Yi LEE
  • Patent number: 11940645
    Abstract: A front light module includes a reflective display device, a front light guide, and a light emitting unit plate. The front light guide plate includes a micro-structure. The micro-structure has a first angle between a surface thereof close to the light emitting unit and an upper surface of the front light guide plate. The micro-structure has a second angle between a surface thereof away from the light emitting unit and the upper surface of the front light guide plate. The micro-structure has a third angle between the surface thereof close to the light emitting unit and the surface thereof away from the light emitting unit. The first angle is within a range between 30 degrees and 60 degrees, the second angle is within a range between 30 degrees and 59 degrees, and the third angle is greater than 90 degrees.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: March 26, 2024
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventors: Chun-Te Wang, Yu-Shan Shen, Yen-Lung Chen
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11935271
    Abstract: A method, computer program, or computer system is provided for compressing a neural network model. One or more blocks are identified from among a superblock corresponding to a multi-dimensional tensor associated with a neural network. A set of weight coefficients associated with the superblock is unified. A model of the neural network is compressed based on the unified set of weight coefficients.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: March 19, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Wei Jiang, Wei Wang, Shan Liu
  • Publication number: 20240090190
    Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Patent number: 11917162
    Abstract: Aspects of the disclosure provide a method and an apparatus for video encoding. The apparatus includes processing circuitry configured to generate an initial feature representation from an input image to be encoded and perform an iterative update of values of a plurality of elements in the initial feature representation. The iterative update includes generate a coded representation corresponding to a final feature representation based on the final feature representation that has been updated from the initial feature representation by a number of iterations of the iterative update. A reconstructed image corresponding to the final feature representation is generated based on the coded representation. An encoded image corresponding to the final feature representation having updated values of the plurality of elements is generated. One of (i) a rate-distortion loss corresponding to the final feature representation or (ii) the number of iterations of the iterative update satisfies a pre-determined condition.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: February 27, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Ding Ding, Sheng Lin, Wei Jiang, Wei Wang, Shan Liu
  • Patent number: 11917154
    Abstract: End-to-end neural image compression using deep reinforcement learning (DRL) is performed by at least one processor and includes encoding an input, generating encoded representations of the input, generating a set of quantization keys using a first neural network, based on a set of previous quantization states, wherein each quantization key in the set of quantization keys and each previous quantization state in the set of previous quantization states correspond to the encoded representations of the input, generating a set of dequantized numbers representing dequantized representations of the encoded representations of the input, based on the set of quantization keys, using a second neural network, and generating a reconstructed output, based on the set of dequantized numbers.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 27, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Wei Jiang, Wei Wang, Sheng Lin, Shan Liu
  • Patent number: 11915457
    Abstract: A method of adaptive neural image compression with rate control by meta-learning includes receiving an input image and a hyperparameter; and encoding the received input image, based on the received hyperparameter, using an encoding neural network, to generate a compressed representation. The encoding includes performing a first shared encoding on the received input image, using a first shared encoding layer having first shared encoding parameters, performing a first adaptive encoding on the received input image, using a first adaptive encoding layer having first adaptive encoding parameters, combining the first shared encoded input image and the first adaptive encoded input image, to generate a first combined output, and performing a second shared encoding on the first combined output, using a second shared encoding layer having second shared encoding parameters.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: February 27, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Wei Jiang, Wei Wang, Shan Liu
  • Patent number: 11914540
    Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: February 27, 2024
    Assignee: Lemon Inc.
    Inventors: Yimin Chen, Shan Lu, Chuang Zhang, Junmou Zhang, Yuanlin Cheng, Jian Wang
  • Patent number: 11901908
    Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Kameran Azadet, Yu-Shan Wang, Hundo Shin, Martin Clara
  • Patent number: 11889852
    Abstract: A Stevia extract made from leaves of the Stevia rebaudiana plant is described. The extract has desired levels of steviol glycosides and is useful in food, beverage, and other consumable products.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: February 6, 2024
    Assignee: PURECIRCLE SDN BHD
    Inventors: Avetik Markosyan, Shan Wang Li, Yu Cheng Bu
  • Patent number: 11864376
    Abstract: A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan Wang, Shun-Yi Lee
  • Publication number: 20230403979
    Abstract: The present invention discloses a ground inclination stereo profiling apparatus and method for a mechanical weeding component, and relates to the field of green agriculture. The ground inclination stereo profiling apparatus for the mechanical weeding component includes a rack assembly, an operation depth and inclination intelligent perception and feedback system, a hydraulic depth adjusting system and a control assembly.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventors: ShanShan YU, Shan Shan WANG
  • Publication number: 20230393467
    Abstract: A method for manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. The photoresist composition includes a photoactive compound and a resin comprising a radical-active functional group and an acid labile group.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 7, 2023
    Inventors: Siao-Shan WANG, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20230387902
    Abstract: A driver circuit is for driving a GaN power commutation switch of a switch mode power converter. A sensing component is connected to the GaN switch for sensing a parameter such as a peak current of the power commutation. An energy storage component provides a certain turn on voltage between the gate and source of the GaN switch. The charging and discharging of the energy storage component is regulated, and the sensing is disabled with timing which is synchronized with the charging and discharging function of the energy storage component. It is prevented that a voltage across the sensing component reduces the generated gate-source drive voltage of the GaN switch.
    Type: Application
    Filed: October 22, 2021
    Publication date: November 30, 2023
    Inventors: ZHIQUAN CHEN, JIE FU, YU WANG, SHAN WANG, GANG WANG, FENG JU
  • Patent number: 11817355
    Abstract: A semiconductor device includes a substrate; a gate structure, located over the substrate, the gate structure including a first gate oxide layer, a second gate oxide layer, and a silicon layer. The first gate oxide layer is over the substrate, and the first gate oxide layer has a sloped sidewall on one side and a vertical sidewall on another side. The second gate oxide layer is over the substrate and on the sloped sidewall of the first gate oxide layer, and a thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer. The silicon layer is formed over the first gate oxide layer and the second gate oxide layer.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: November 14, 2023
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Hu Wang, Shan Shan Wang, Feng Qiu, Wei Hu Zhang
  • Patent number: 11804424
    Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: October 31, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang