Patents by Inventor Shane Charles Hollmer
Shane Charles Hollmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8107273Abstract: An integrated circuit may include multiple programmable metallization cells (PMCs) and a multiple bit lines. Each bit line may be connected to a anodes of a different set of PMCs, and provide a read data path from a selected one of the set of PMCs. Access devices may each provide a controllable impedance path between at least one cathode and a common source node.Type: GrantFiled: July 23, 2009Date of Patent: January 31, 2012Assignee: Adesto Technologies CorporationInventors: Shane Charles Hollmer, Nad Edward Gilbert
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Patent number: 6593606Abstract: An array of memory cells includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . wherein each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts, and wherein contacts overlying a first bit line are staggered with respect to contacts overlying a second bit line that is adjacent to the first bit line.Type: GrantFiled: November 22, 2000Date of Patent: July 15, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Mark W. Randolph, Shane Charles Hollmer, Pau-Ling Chen, Richard M. Fastow
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Patent number: 6538270Abstract: An array of memory cells that includes a plurality of memory cells interconnected via a grid of wordlines and bitlines, wherein each of the bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , and wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts and wherein a column of the bitlines has a first discontinuous and a second discontinuous bitline that are separated from one another by a distance &Dgr;.Type: GrantFiled: November 22, 2000Date of Patent: March 25, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Mark W. Randolph, Shane Charles Hollmer, Pau-Ling Chen, Richard M. Fastow
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Patent number: 6275414Abstract: An array of memory cells that includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . and each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts and a select transistor is formed every P wordlines, wherein P is greater than N.Type: GrantFiled: November 22, 2000Date of Patent: August 14, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Mark W. Randolph, Shane Charles Hollmer, Pau-Ling Chen, Richard M. Fastow
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Patent number: 6266275Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground.Type: GrantFiled: September 30, 1999Date of Patent: July 24, 2001Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Paul-Ling Chen, Mike Van Buskirk, Shane Charles Hollmer, Binh Quang Le, Shoichi Kawamura, Chung-You Hu, Yu Sun, Sameer Haddad, Chi Chang
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Patent number: 6262469Abstract: A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.Type: GrantFiled: March 25, 1998Date of Patent: July 17, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Binh Quang Le, Pau-Ling Chen, Shane Charles Hollmer
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Patent number: 6141244Abstract: A method and circuit for sensing multi states of a NAND memory cell by applying plurality of external sensing bias current at a constant positive gate and bias voltage and detecting a cell current wherein the cell current depends upon the state of the memory cell.Type: GrantFiled: September 2, 1999Date of Patent: October 31, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Joseph G. Pawletko, Pau-Ling Chen, Shane Charles Hollmer
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Patent number: 6072725Abstract: A method and an apparatus are provided for the production and supply of an erase voltage for the initial erasing operation of a floating gate transistor used as a capacitor in a voltage regulator, along with the proper electrical connection of the capacitor's control gate and commonly connected regions. In one embodiment, a capacitor erase control circuit controls a pass transistor for connecting the control gate of the floating gate capacitor to ground and another pass transistor for isolating the commonly connected source, drain and channel regions of the floating gate capacitor (the "well node") from ground. The erase control circuit simultaneously applies a capacitor erase input and a clock input to an erase voltage pass circuit to control a third pass transistor to apply an erase voltage to the well node, thereby erasing the floating gate capacitor.Type: GrantFiled: January 26, 1999Date of Patent: June 6, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Binh Quang Le, Shane Charles Hollmer, Pau-ling Chen
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Patent number: 5999452Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground.Type: GrantFiled: April 21, 1998Date of Patent: December 7, 1999Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Pau-Ling Chen, Mike Van Buskirk, Shane Charles Hollmer, Binh Quang Le, Shoichi Kawamura, Chung-You Hu, Yu Sun, Sameer Haddad, Chi Chang
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Patent number: 5939928Abstract: In a high voltage pass gate suitable for use as a block decoder in a flash memory circuit, the boosting of the block decoder's internal nodes is performed using coupling capacitors and boost transistors which are decoupled from the high capacitance pass gate node. The block decoder uses three internal block decoder nodes. Each of the three nodes is held to ground by a corresponding discharge transistor when the block is unselected. Each of the three nodes of a selected block is discharged to a normal supply voltage by a corresponding diode-connected regulation transistor when the high voltage supply is turned off after a programming operation has finished. Each of the three nodes has a separate coupling capacitor associated with it. One of the nodes is connected to the gates of the high voltage pass transistors, this node has high capacitance. The remaining two nodes have relatively small coupling capacitors.Type: GrantFiled: August 19, 1997Date of Patent: August 17, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Binh Quang Le, Pau-Ling Chen, Shane Charles Hollmer
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Patent number: 5912489Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground.Type: GrantFiled: September 30, 1997Date of Patent: June 15, 1999Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Pau-Ling Chen, Mike Van Buskirk, Shane Charles Hollmer, Binh Quang Le, Shoichi Kawamura, Chung-You Hu, Yu Sun, Sameer Haddad, Chi Chang
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Patent number: 5909396Abstract: According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistor's threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps.Type: GrantFiled: August 3, 1998Date of Patent: June 1, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Binh Quang Le, Pau-Ling Chen, Shane Charles Hollmer, Chung-You Hu, Narbeh Derhacobian
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Patent number: 5852576Abstract: Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply.Type: GrantFiled: October 6, 1997Date of Patent: December 22, 1998Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Binh Quang Le, Pau-Ling Chen, Shane Charles Hollmer, Shoichi Kawamura, Michael Shingche Chung, Vincent C. Leung, Masaru Yano
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Patent number: 5844840Abstract: According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps.Type: GrantFiled: August 19, 1997Date of Patent: December 1, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Binh Quang Le, Pau-Ling Chen, Shane Charles Hollmer, Chung-You Hu, Narbeh Derhacobian