Patents by Inventor Shanthi Pavan

Shanthi Pavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111732
    Abstract: Embodiments may relate to a circuit for use in an analog-to-digital converter (ADC) circuit. The circuit may include a first residue amplifier stage and a second residue amplifier stage. The circuit may further include a synthesized delay stage with a digital-to-analog converter (DAC) electrically positioned between a signal input and the input of the second residue amplifier stage. The circuit may further include a resistor electrically positioned between the signal input and the input of the second residue amplifier stage. Other embodiments may be described or claimed.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Applicant: Analog Devices International Unlimited Company
    Inventors: Shanthi Pavan YENDLURI, Hajime SHIBATA
  • Patent number: 10958281
    Abstract: Embodiments may relate to a circuit for use in an analog-to-digital converter (ADC) circuit. The circuit may include a first residue amplifier stage and a second residue amplifier stage. The circuit may further include a synthesized delay stage with a digital-to-analog converter (DAC) electrically positioned between a signal input and the input of the second residue amplifier stage. The circuit may further include a resistor electrically positioned between the signal input and the input of the second residue amplifier stage. Other embodiments may be described or claimed.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 23, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Shanthi Pavan Yendluri, Hajime Shibata
  • Patent number: 10432210
    Abstract: Continuous-time pipeline analog-to-digital converters can achieve excellent performance, and avoid sampling-related artifacts traditionally associated with discrete-time pipeline ADCs. However, the continuous-time circuitry in the ADCs can pose a challenge for digital signal reconstruction, since the transfer characteristics of the continuous-time circuitry are not as well characterized or as simple as their discrete-time counterparts. To achieve perfect digital signal reconstruction, special techniques are used to implement an effective and efficient digital filter that combines the digital output signals from the stages of the CT ADCs.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 1, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Shanthi Pavan Yendluri, Donald W. Paterson, Victor Kozlov, Hajime Shibata
  • Patent number: 10361711
    Abstract: Residue generation systems for use in continuous-time and hybrid ADCs are disclosed. An example residue generation system includes at least one stub filter, configured to generate a modified analog input based on an analog input, and a quantizer, configured to generate a digital input to a feedforward DAC based on the modified analog input generated by the filter. The feedforward DAC is configured to generate a feedforward path analog output based on the digital input generated by the quantizer, and the system may further be configured to generate a residue signal based on the feedforward path analog output. Providing one or more stub filters that filter the analog input before it is quantized by the quantizer advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 23, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Shanthi Pavan Yendluri, Hajime Shibata, Christopher W. Mangelsdorf
  • Patent number: 9835647
    Abstract: Apparatus and methods for interfacing with a micro-electromechanical system (MEMS) sensor are provided. In an example, an apparatus can interface circuit including an integrator circuit, a sample switch circuit, a saturation detector and a controller. The saturation detector can be configured to receive a signal indicative of an integration of charge of the sensor, to compare the signal indicative of the integration of charge to an integrator saturation threshold and to modulate a divide parameter using the comparison of the signal indicative of the integration of charge and the integrator saturation threshold. The controller can be configured to receive a clock signal and to control the sample switch circuit based on a phase of the clock signal and the divide parameter.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 5, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ion Opris, Justin Seng, Shanthi Pavan, Marwan Ashkar, Michelle Lee
  • Patent number: 9644963
    Abstract: This application discusses simplified interface circuits for a gyroscope. In an example, an interface can include an automatic gain control (AGC) circuit configured to couple to driver for a proof mass of a gyroscope sensor and to drive the proof-mass to oscillate at a predefined oscillation amplitude, and a phase-locked loop (PLL) configured to receive sensed oscillation information from the proof-mass and to provide at least a first phase signal synchronized with a sinusoidal waveform of the sensed oscillation information.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 9, 2017
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Shungneng Lee, Hai Tao, Ion Opris, Shanthi Pavan
  • Publication number: 20160161256
    Abstract: This application discusses, among other things, simplified interface circuits for a gyroscope. In an example, a interface can include an automatic gain control (AGC) circuit configured to couple to driver for a proof mass of a gyroscope sensor and to drive the proof-mass to oscillate at a predefined oscillation amplitude, and a phase-locked loop (PLL) configured to receive sensed oscillation information from the proof-mass and to provide at least a first phase signal synchronized with a sinusoidal waveform of the sensed oscillation information.
    Type: Application
    Filed: March 18, 2014
    Publication date: June 9, 2016
    Inventors: Shungneng Lee, Hai Tao, Ion Opris, Shanthi Pavan
  • Publication number: 20150268284
    Abstract: Apparatus and methods for interfacing with a micro-electromechanical system (MEMS) sensor are provided. In an example, an apparatus can interface circuit including an integrator circuit, a sample switch circuit, a saturation detector and a controller. The saturation detector can be configured to receive a signal indicative of an integration of charge of the sensor, to compare the signal indicative of the integration of charge to an integrator saturation threshold and to modulate a divide parameter using the comparison of the signal indicative of the integration of charge and the integrator saturation threshold. The controller can be configured to receive a clock signal and to control the sample switch circuit based on a phase of the clock signal and the divide parameter.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 24, 2015
    Inventors: Ion Opris, Justin Seng, Shanthi Pavan, Marwan Ashkar, Michelle Lee
  • Patent number: 9000839
    Abstract: An integrated continuous-time active-RC filter comprises a set of opamp integrators with Operational Transconductance Amplifiers (OTAs), and at least one assistant transconductor connected between an input and an output of each of the integrators of the set; wherein the assistant transconductor comprises a plurality of sets of MOSFETS connected in parallel to each other wherein each set of MOSFETS is formed by a pair of MOSFETs connected in series, with one MOSFET of the pair operating in the triode region and the other MOSFET of the pair operating in the saturation region; and wherein the assistant transconductor is configured to inject an assistant current into the output of each of the integrators in the set to enhance the linearity and speed of the opamp integrators of the set.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 7, 2015
    Assignees: The Secretary, Department of Information and Technology, Indian Institute of Technology, Madras
    Inventors: Shanthi Pavan Yendluri, Siva Viswanathan Thyagarajan
  • Publication number: 20130222054
    Abstract: An integrated continuous-time active-RC filter comprises a set of opamp integrators with Operational Transconductance Amplifiers (OTAs). The filter further includes at least one assistant connected between the input and output of each of the integrators of the set to enhance the linearity and speed of the opamp integrators of the set. The assistant comprises a plurality of sets of transconductors connected in parallel to each other wherein each set of transconductors is formed by a pair of MOSFETs connected in series, with one MOSFET operating in the triode region and the other MOSFET operating in the saturation region. The assistant is configured to provide an assistant current to be injected into the source of each of the integrators in the set to enhance the linearity and speed of the opamp integrators of the set.
    Type: Application
    Filed: September 2, 2011
    Publication date: August 29, 2013
    Applicants: Indian Institute of Technology, Madras, The Secretary, Department of Information and Technology (DIT)
    Inventors: Shanthi Pavan Yendluri, Siva Viswanathan Thyagarajan
  • Patent number: 7738547
    Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: June 15, 2010
    Assignee: Vitesse Semiconductor Corporation
    Inventors: John S. Wang, Sudeep Bhoja, Shanthi Pavan
  • Patent number: 7471751
    Abstract: Methods, apparatuses, and systems are presented for performing channel equalization comprising receiving a signal from a channel associated with inter-symbol interference, processing the received signal to effectively apply a plurality of linearly independent impulse responses to the received signal to produce a plurality of intermediate signals, scaling each of the intermediate signals by each of a plurality of multiplier factors to produce a plurality of scaled signals, and combining the scaled signals to produce a resulting signal corresponding to an equalized version of the received signal in order to reduce effects of inter-symbol interference.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: December 30, 2008
    Assignee: Vitesse Semiconductor Corporation
    Inventor: Shanthi Pavan
  • Publication number: 20080260015
    Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.
    Type: Application
    Filed: November 20, 2007
    Publication date: October 23, 2008
    Inventors: John S. Wang, Sudeep Bhoja, Shanthi Pavan
  • Patent number: 7301997
    Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.
    Type: Grant
    Filed: September 11, 2001
    Date of Patent: November 27, 2007
    Assignee: Vitesse Semiconductor Corporation
    Inventors: John S Wang, Sudeep Bhoja, Shanthi Pavan
  • Patent number: 7142596
    Abstract: Methods, apparatuses, and systems are presented for performing channel equalization involving receiving a signal from a channel associated with inter-s interference (ISI), providing the received signal to an inductor, capacitor, resistance (LCR) network comprising a plurality of inductors and a plurality of capacitors, generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal, applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals, and generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: November 28, 2006
    Assignees: Vitesse Semiconductor Corporation, Indian Institute of Technology
    Inventor: Shanthi Pavan
  • Patent number: 7003228
    Abstract: Improved high-speed adaptive equalization is presented that may involve converting an optical signal into an electrical signal and performing equalization by (i) filtering the electrical signal with an analog filter according to at least one filter coefficient to produce a filtered output, (ii) generating an error signal from the filtered output according to an error function, (iii) providing at least one control signal to the analog filter for adjusting the at least one filter coefficient, (iv) detecting a relationship between a change in the at least one filter coefficient and a change in the error signal, and (v) adjusting the at least one filter coefficient according to the relationship to minimize the error signal. The least one coefficient may comprise a plurality of coefficients, and the relationship may be a gradient estimate having multiple components, each determined by varying only one of the coefficients and detecting a resulting change in the error signal.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 21, 2006
    Assignee: Vitesse Semiconductor Corporation
    Inventors: John S. Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao
  • Publication number: 20050281364
    Abstract: Methods, apparatuses, and systems are presented for performing channel equalization comprising receiving a signal from a channel associated with inter-symbol interference, processing the received signal to effectively apply a plurality of linearly independent impulse responses to the received signal to produce a plurality of intermediate signals, scaling each of the intermediate signals by each of a plurality of multiplier factors to produce a plurality of scaled signals, and combining the scaled signals to produce a resulting signal corresponding to an equalized version of the received signal in order to reduce effects of inter-symbol interference.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 22, 2005
    Applicants: BIG BEAR NETWORKS, Indian Institute of Technology
    Inventor: Shanthi Pavan
  • Publication number: 20050281362
    Abstract: Methods, apparatuses, and systems are presented for performing channel equalization involving receiving a signal from a channel associated with inter-symbol interference (ISI), providing the received signal to an LCR network comprising a plurality of inductors and a plurality of capacitors, generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal, applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals, and generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 22, 2005
    Applicants: Big Bear Networks, Indian Institute of Technology
    Inventor: Shanthi Pavan
  • Publication number: 20040136731
    Abstract: Improved high-speed adaptive equalization is presented that may involve converting an optical signal into an electrical signal and performing equalization by (i) filtering the electrical signal with an analog filter according to at least one filter coefficient to produce a filtered output, (ii) generating an error signal from the filtered output according to an error function, (iii) providing at least one control signal to the analog filter for adjusting the at least one filter coefficient, (iv) detecting a relationship between a change in the at least one filter coefficient and a change in the error signal, and (v) adjusting the at least one filter coefficient according to the relationship to minimize the error signal. The least one coefficient may comprise a plurality of coefficients, and the relationship may be a gradient estimate having multiple components, each determined by varying only one of the coefficients and detecting a resulting change in the error signal.
    Type: Application
    Filed: September 30, 2003
    Publication date: July 15, 2004
    Applicant: Big Bear Networks, Inc.
    Inventors: John S. Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao
  • Patent number: 6552615
    Abstract: A method and system to compensate for DC and low frequency current produced by a photodiode that is illuminated with an optical data stream is described. An optical data stream ideally produces no current from a photodiode when the bit is a 0 and produces a current proportional to the optical power when the bit is a 1. Thus, the current produced from the photodiode consists of a DC component, which is typically half the current of a 1 bit (if there is an equal number of 1s and 0s in the data), and a high frequency component that carries the data. The DC component can interfere with the signal path's ability to process the information carrying component of the photodiode current, by causing a fixed offset to propagate and be amplified through it. This offset distorts the voltage signal at the output of the signal path, and must therefore be cancelled early in the path; usually in the first transimpedance stage or just after it.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: April 22, 2003
    Assignee: Big Bear Networks, Inc.
    Inventors: Shanthi Pavan, Arvin Shahani