Abstract: Method and system for a programmable analog tapped delay line filter are disclosed. One embodiment of the present invention is a programmable analog tapped delay line filter comprising an input line, an output line, and one or more gaincells or taps coupled between the input line and the output line. The input and output lines each comprises a cascade of one or more differential delay cells, and each of the one or more gaincells or taps corresponds to a tap weight or coefficient. Furthermore, the input and output lines are terminated in impedances and the filter produces one or more outputs.

Abstract: A transconductance bias circuit includes: a differential pair having a first transistor M14 and a second transistor M15; a resistor R coupled between a gate of the first transistor M14 and a gate of the second transistor M15, the gate of the first transistor M14 is coupled to a reference voltage node; a third transistor M10 coupled to the first transistor M14; a fourth transistor M11 coupled to the second transistor M15; a fifth transistor M8 coupled to the third transistor M10, a gate of the fifth transistor M8 is coupled to the reference voltage node; a sixth transistor M9 coupled to the fourth transistor M11, a gate of the sixth transistor M9 is coupled to the reference voltage node; a current mirror 22 coupled to the fifth and sixth transistors M8 and M9; and a seventh transistor M6 coupled to the fourth transistor M11, a current in the seventh transistor M6 is equal to a current in the resistor R.

Abstract: A circuit 100, which can be used to perform a sample and hold function, includes a switch 112 with a current patch coupled between an input node VIN and an output node VOUT. A capacitor 114 is coupled to the output node VOUT. A replica device 160 includes a current path coupled between the input node VIN and a supply voltage node VDD. A bootstrap circuit, e.g., including a bootstrap capacitor 164, is coupled between a control terminal of the first switch 112 and a control terminal of the replica device 160.

Abstract: A transconductance bias circuit includes: a differential pair having a first transistor M14 and a second transistor M15; a resistor R coupled between a gate of the first transistor M14 and a gate of the second transistor M15, the gate of the first transistor M14 is coupled to a reference voltage node; a third transistor M10 coupled to the first transistor M14; a fourth transistor M11 coupled to the second transistor M15; a fifth transistor M8 coupled to the third transistor M10, a gate of the fifth transistor M8 is coupled to the reference voltage node; a sixth transistor M9 coupled to the fourth transistor M11, a gate of the sixth transistor M9 is coupled to the reference voltage node; a current mirror 22 coupled to the fifth and sixth transistors M8 and M9; and a seventh transistor M6 coupled to the fourth transistor M11, a current in the seventh transistor M6 is equal to a current in the resistor R.

Abstract: A high Q bandpass filter (102) is tuned by applying a transient (204) to the filter to cause it to ring. The ringing of the filter produces an output damped oscillatory waveform (206) whose zero crossings (208) are converted to a pulse train (210) and counted in a digital counter (112) to a predetermined number n. The output (214) of the counter is compared to an accurate timing signal (216) which has a time duration equal to the time of n pulses when the filter is accurately tuned. The output of the comparator (118) is applied to an integrator (122) to generate a control signal V.sub.c to tune the filter. The high frequency tuning problem is thus converted to a low frequency, time domain problem which is readily implemented.