Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.

Abstract: A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.

Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.

Abstract: A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.

Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.

Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.

Abstract: An operating circuit is provided. A first N-type transistor determines whether to turn the path between a core circuit and a ground terminal on or off according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific circuit according to the first detection signal.

Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.

Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Abstract: A voltage regulation circuit is suitable to provide an output voltage to a core circuit. The voltage regulation circuit includes a pad, a pull-low unit, a first controlling unit, a second controlling unit and a voltage regulation circuit. The pad receives and provides an input voltage. The pull-low unit generates a pull-low voltage according to the input voltage. The first controlling unit generates a first controlling signal according to the input voltage and the pull-low voltage. The second controlling unit generates a second controlling signal according to the input voltage and the first controlling signal. The voltage regulation unit regulates the input voltage according to the first controlling signal and the second controlling signal, so as to generate the output voltage.

Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.

Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.

Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. A detector is coupled between a first input-output pad and a second input-output pad and detects the voltage levels of the first and second input-output pads to generate a detection signal. A inverter generates a control signal according to the detection signal. A control element is coupled between the first input-output pad and a first node. A current release element is coupled between the first node and the second input-output pad. When the detection signal is at a specific level, the control element and the current release element provide a discharge path to release an ESD current from the first input-output pad to the second input-output pad. When the detection signal is not at the specific level, the control element and the current release element do not provide a discharge path.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.