Abstract: A driver circuit has a pad that may be utilized for programming a core circuit or receiving a data signal. A trace high circuit receives a pad voltage signal from the pad, and outputs a trace high voltage approximating a higher voltage of the pad voltage signal and the power supply voltage. A level shifter and a first inverter output a pull high control signal generated by inverting and level shifting a programming control signal. An ESD blocking circuit selectively blocks the pad voltage signal from reaching the core circuit depending on the pad voltage signal and the level-shifted programming control signal. A pull high circuit receives the pull high control signal and the power supply voltage, and outputs the power supply voltage to the core circuit when the pull high control signal is lower than the power supply voltage.

Abstract: Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving device performance. The SOI devices may be used in full depletion type transistors or partial depletion type transistors.

Abstract: A pad circuit includes a pad, a gate driving circuit, a voltage selection circuit, and an ESD detection/avoiding circuit. The gate driving circuit is used to discharge the ESD induced current. The ESD detection/avoiding circuit is used to isolate the ESD induced voltage. The voltage selection circuit selects a higher voltage from a power/ground terminal and the pad and outputs it to the gate driving circuit, so that the pad circuit can be used for the programming and 1/0 operations.

Abstract: When an electrostatic discharge event occurs to a connection pad of a chip, an electrostatic discharge detector layout in a feedback loop is able to detect an induced electrostatic discharge voltage for generating a control signal. A pass transistor can be turned off by the control signal for isolating the induced electrostatic discharge voltage, and the internal circuit of the chip can be protected from being damaged by the induced electrostatic discharge voltage. Furthermore, the designed circuit based on electrostatic discharge isolation technique for protecting the internal circuit of the chip is compatible with programmable circuits, and the connection pad can be furnished with burning signals or logic signals.

Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

Abstract: The present invention discloses a tie-off circuit coupled between a first potential and a gate of a MOS device whose source is connected to a second potential. The tie-off circuit includes at least one resistor and at least on diode. The resistor is coupled between the gate of the MOS device and the first potential for preventing the gate of the MOS device from floating during a normal circuit operation. The diode is coupled between the gate of the MOS device and the first potential, in parallel with the resistor, for reducing a voltage difference across a gate oxide layer of the MOS device during an electrostatic discharge (ESD) event, thereby protecting the same from ESD damage.

Abstract: An ESD avoiding circuit includes a first ESD protection unit, an ESD detection unit, a switch unit, and an RC filter unit. The first ESD protection unit transmits an ESD current between a first conducting path and a second conducting path. The ESD detection unit is coupled to the first conducting path. The ESD detection unit includes an input terminal, and an output terminal coupled to the first ESD protection unit for detecting an ESD and controlling the first ESD protection unit to conduct the ESD current according to a detection result. The switch unit is coupled between the first conducting path and a core circuit and conducts the first conducting path to the core circuit according to signals of the input terminal and the output terminal of the ESD detection unit. The RC filter unit couples a first voltage to the input terminal of the ESD detection unit.

Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.

Abstract: A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.

Abstract: A non-volatile memory cell includes an ion well of a semiconductor substrate; a first half-transistor having a firs select gate, a first diffusion region in the ion well, and a first gate dielectric layer between the first select gate and the ion well; a second half-transistor disposed adjacent to the first half-transistor, wherein the second half-transistor has a second select gate spaced apart from the first select gate, a second diffusion region in the ion well, and a second gate dielectric layer between the second select gate and the ion well. The first and second half-transistors are mirror-symmetrical to each other.

Abstract: A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.

Abstract: An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell tha

Abstract: An ESD avoiding circuit includes a first ESD protection unit, an ESD detection unit, a switch unit, and an RC filter unit. The first ESD protection unit transmits an ESD current between a first conducting path and a second conducting path. The ESD detection unit is coupled to the first conducting path. The ESD detection unit includes an input terminal, and an output terminal coupled to the first ESD protection unit for detecting an ESD and controlling the first ESD protection unit to conduct the ESD current according to a detection result. The switch unit is coupled between the first conducting path and a core circuit and conducts the first conducting path to the core circuit according to signals of the input terminal and the output terminal of the ESD detection unit. The RC filter unit couples a first voltage to the input terminal of the ESD detection unit.

Abstract: When an electrostatic discharge event occurs to a connection pad of a chip, an electrostatic discharge detector layout in a feedback loop is able to detect an induced electrostatic discharge voltage for generating a control signal. A pass transistor can be turned off by the control signal for isolating the induced electrostatic discharge voltage, and the internal circuit of the chip can be protected from being damaged by the induced electrostatic discharge voltage. Furthermore, the designed circuit based on electrostatic discharge isolation technique for protecting the internal circuit of the chip is compatible with programmable circuits, and the connection pad can be furnished with burning signals or logic signals.

Abstract: Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving device performance. The SOI devices may be used in full depletion type transistors or partial depletion type transistors.

Abstract: An electrostatic discharge (ESD) avoiding circuit comprises an ESD detecting unit and a switch unit. The ESD detecting unit is coupled to a first conductive path for detecting whether the ESD happened or not. The switch unit is coupled between the first conductive path and a core circuit for switching whether the first conductive path is conducted to the core circuit or not according to a detection result of the ESD detecting unit. The ESD avoiding circuit can avoid an electrostatic current transmitting to the core circuit when the ESD is happened, and the ESD avoiding circuit can make the normal signal/voltage providing to the core circuit for operating when the ESD isn't happened.

Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.

Abstract: Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving device performance. The SOI devices may be used in full depletion type transistors or partial depletion type transistors.

Abstract: An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell tha

Abstract: Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.