Abstract: A digital interconnect system transmits pulses across a differential transmission line in response to transitions in an input data signal.

Abstract: In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.

Abstract: A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.

Abstract: In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.

Abstract: Leakage power consumed by an integrated circuit is estimated as the difference between total power consumption and a nominal expected power consumption. Leakage power is reduced by cooling the integrated circuit in an active cooling system. By expending power in the active cooling system, the integrated circuit is cooled and the total power consumption is decreased. When the decrease in total power consumption is greater than the power expended in the cooling system, an overall power savings is achieved.

Abstract: The disclosure describes packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.

Abstract: In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.

Abstract: A synchronous clock generator for an integrated circuit is described in which a delay lock loop circuit may be used to delay a first input signal. A delay circuit is coupled to the delay lock loop circuit and receives a control voltage from the delay lock loop circuit, which is used to delay a second input signal. The first and second input signal may be complimentary.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.

Abstract: In general, in one aspect, the disclosure describes a method for use in tracking received out-of-order packets. Such a method can include receiving at least a portion of a packet that includes data identifying an order within a sequence, and based on the data identifying the order, requesting stored data identifying a set of contiguous previously received out-of-order packets having an ordering within the sequence that borders the received packet.

Abstract: A light-emitting device and optical communication system based on the light-emitting device is disclosed. The light-emitting device is formed in a float-zone substrate. The light-emitting device includes on the substrate lower surface a reflective layer and on the upper surface spaced apart doped regions. The portion of the upper surface between the doped regions is textured and optionally covered with an antireflection coating to enhance light emission. The light-emitting device can operate as a laser or as a light-emitting diode, depending on the reflectivities of the antireflection coating and the reflective layer.

Abstract: A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.

Abstract: One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.

Abstract: A digital interconnect system transmits pulses across a differential transmission line in response to transitions in an input data signal.

Abstract: A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

Abstract: In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.

Abstract: A receiver integrated circuit (IC) die or functional unit has deskew circuitry to reduce bit-to-bit timing variation that is no more than one bit time interval in a number of bits that are received, before validating the capture of the bits using a transition in a received strobe signal. The data bits and the strobe signal are driven in a parallel bus section that may be part of a shared multi-drop bus or a point-to-point bus. The system applications include interfacing to a processor or memory bus of a computer system.

Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

Abstract: In some embodiments, the invention includes a system having a processor and control circuitry. The control circuitry controls a setting of a body bias signal to control body biases provided in the processor to at least partially control a parameter of the processor, wherein the control circuitry controls the setting responsive to processor signal resulting for execution of software. The control circuitry may further control settings of a supply voltage signal and a clock signal to control the parameter. More than one parameter may be controlled. Examples of the parameters include performance, power consumption, and temperature.