Patents by Inventor Sheldon Aronowitz

Sheldon Aronowitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5296386
    Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.
    Type: Grant
    Filed: March 6, 1991
    Date of Patent: March 22, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney Hart, Court Skinner
  • Patent number: 5292402
    Abstract: Materials of the lead perovskite family PbZr.sub.x Ti.sub.1-x O.sub.3 have been discovered to be excellent masking materials in the etching of silicon and silicon-containing materials with chlorine and fluorine -based plasmas. Generally, materials of the lead perovskite family are suitable masking materials for any material that is etched in chlorine and fluorine -based plasmas.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: March 8, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Norman E. Abt, Sheldon Aronowitz
  • Patent number: 5280185
    Abstract: A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: January 18, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Sung T. Ahn
  • Patent number: 5192712
    Abstract: A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur. Aluminum diffusion is modified by the presence of the germanium so that channeling and out diffusion are controlled. The control is enhanced when boron is incorporated into the silicon along with the aluminum.
    Type: Grant
    Filed: April 15, 1992
    Date of Patent: March 9, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Amolak Ramde
  • Patent number: 5137838
    Abstract: A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along with germanium, which is in sufficient concentration to inhibit impurity diffusion in the silicon epitaxial layer. This inhibition effect has been found to be sufficient to cause the combination of boron and gallium to act as slow diffusers. The result is that the performance of arsenic and antimony, in the creation of buried layers for NPN transistors. Thus, the performance of NPN transistors can be matched for PNP transistors. This means that an IC can be fabricated so that more nearly equal performance NPN and PNP transistors can be fabricated simultaneously in a common substrate.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: August 11, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Amolak Ramde, Sheldon Aronowitz
  • Patent number: 5095358
    Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
    Type: Grant
    Filed: April 18, 1990
    Date of Patent: March 10, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Sung T. Ahn
  • Patent number: 5043292
    Abstract: A self-aligned masking process for use with ultra-high energy implants (implant energies equal to or greater than 1 MeV) is provided. The process can be applied to an arbitrary range of implant energies. Consequently, high doses of dopant may be implanted to give high concentrations that are deeply buried. This can be coupled with the fact that amorphization of the substrate lattice is relatively localized to the region where the ultra-high energy implant has peaked to yield a procedure to form buried, localized isolation structures.
    Type: Grant
    Filed: May 31, 1990
    Date of Patent: August 27, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Matthew Buynoski
  • Patent number: 4985717
    Abstract: A semiconductor memory device having a CMOS memory cell with a floating gate and increasing concentration of dopant in the source, drain and channel regions. Typically the concentration profile is generally exponential across the channel width. The device has relatively high diffusion current densities accelerated toward the surface and directed toward the channel/drain interface. Gate oxidation thickness is reduced over the channel near the drain to create a tunnel "window" in the area of greatest electric field magnitude. The device provides for significantly reduced write times as compared to conventional devices.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: January 15, 1991
    Assignee: National Semiconductor
    Inventors: Sheldon Aronowitz, Donald D. Forsythe, George P. Walker, Bhaskar V. S. Gadepally
  • Patent number: 4746964
    Abstract: One p-type dopant is implanted into a substrate to modify the diffusion characteristics of another p-type dopant implanted into the substrate. As an example, gallium is diffused into a p-type region along with boron to confine the diffusion of the boron, and thereby produce smaller device regions in silicon. Along with the confined volume, the resulting regions exhibit electrical activity that is greater than the simple additive behavior of boron and gallium acting alone.
    Type: Grant
    Filed: August 28, 1986
    Date of Patent: May 24, 1988
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Sheldon Aronowitz
  • Patent number: 4689667
    Abstract: A method for preparing semiconductor components having a structure with sharply defined spatial distributions of dopant atoms with control over the degree of electrical activation of the dopant atoms. Control of spatial distribution and the degree of electrical activation of dopant atoms is achieved by implantation of dopant atoms along with rare gas atoms and another type of dopant atom within substantially the same preselected depth boundaries of a silicon or germanium substrate.
    Type: Grant
    Filed: June 11, 1985
    Date of Patent: August 25, 1987
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Sheldon Aronowitz