Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.

Abstract: A method includes following steps. A semiconductor substrate is etched to form semiconductor fins. A dielectric material is deposited into a trench between the semiconductor fins. The semiconductor fins are etched such that top ends of the semiconductor fins are lower than a top surface of the dielectric material. After etching the semiconductor fins, epitaxially growing epitaxial fins on the semiconductor fins, respectively. A chemical mechanical polish (CMP) process is performed on the epitaxial fins, followed by cleaning the epitaxial fins using a non-contact-type cleaning device. The dielectric material is then such that the top surface of the dielectric material is lower than top ends of the epitaxial fins. A gate structure is formed across the epitaxial fins.

Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.

Abstract: A method includes: forming source/drain epitaxy structures over a semiconductor fin; forming a first ILD layer covering the source/drain epitaxy structures; forming a gate structure over the semiconductor fin and between the source/drain epitaxy structures; forming a capping layer over the gate structure; thinning the capping layer; forming a hard mask layer over the capping layer; forming a second ILD layer spanning the hard mask layer and the first ILD layer; forming, by using an etching operation, a contact hole passing through the first and second ILD layers to one of the source/drain epitaxy structures, the etching operation being performed such that the hard mask layer has a notched corner in the contact hole; filling the contact hole with a conductive material; and performing a CMP process on the conductive material until that the notched corner of the hard mask layer is removed.

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Abstract: A CMP slurry composition and a method of polishing a metal layer are provided. In some embodiments, the CMP slurry composition includes about 0.1 to 10 parts by weight of a metal oxide, and about 0.1 to 10 parts by weight of a chelator. The chelator includes a thiol compound or a thiolether compound.

Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

Abstract: A semiconductor substrate has an exposed surface having a compositionally uniform metal, and an embedded surface having the metal and an oxide. The exposed surface is polished using a first slurry including a first abrasive and a first amine-based alkaline until the embedded surface is exposed. The embedded surface is polished using a second slurry including a second abrasive and a second amine-based alkaline. The second abrasive is different from the first abrasive. The second amine-based alkaline is different from the first amine-based alkaline. The metal and the oxide each has a first and a second removal rate in the first slurry, respectively, and a third and fourth removal rate in the second slurry, respectively. A ratio of the first removal rate to the second removal rate is greater than 30:1, and a ratio of the third removal rate to the fourth removal rate is about 1:0.5 to about 1:2.

Abstract: A semiconductor structure is provided, including a conductive layer, a dielectric layer over the conductive layer, a ruthenium material in the dielectric layer and in contact with a portion of the conductive layer, and a ruthenium oxide material in the dielectric layer laterally between the ruthenium material and the dielectric layer.

Abstract: A wafer is polished by performing a chemical reaction to change a property of a first portion of a material layer on the wafer using a first chemical substance. A first rinse is performed to remove the first chemical substance and retard the chemical reaction. A mechanical polishing process is then performed to remove the first portion of the material layer.

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.

Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).

Abstract: A method of manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer; removing a portion of the dielectric layer to form an opening exposing a portion of the conductive layer; filling a ruthenium-containing material in the opening and in contact with the dielectric layer; and polishing the ruthenium-containing material using a slurry including an abrasive and an oxidizer selected from the group consisting of hydrogen peroxide (H2O2), potassium periodate (KIO4), potassium iodate (KIO3), potassium permanganate (KMnO4), iron(III) nitrate (FeNO3) and a combination thereof.

Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

Abstract: The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.

Abstract: A post CMP cleaning apparatus is provided. The post CMP cleaning apparatus includes a cleaning stage. The post CMP cleaning apparatus also includes a rotating platen disposed in the cleaning stage, and the rotating platen is configured to hold and rotate a semiconductor wafer. The post CMP cleaning apparatus further includes a vibrating device disposed over the rotating platen. The post CMP cleaning apparatus further includes a solution delivery module disposed near the vibrating device and configured to deliver a cleaning fluid to the semiconductor wafer. The vibrating device is configured to provide the cleaning fluid with a specific frequency which is at least greater than 100 MHz while the rotating platen is rotating the semiconductor wafer, so that particles on the semiconductor wafer are removed by the cleaning fluid.

Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).

Abstract: The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor.