Abstract: A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads.

Abstract: Systems and methods are provided for performing chemical-mechanical planarization. An example system includes: a polishing head, a polishing pad, a slurry distribution component, and a reactant distribution component. The polishing head is configured to perform chemical-mechanical planarization on an article. The polishing pad is configured to support the article. The slurry distribution component is configured to provide a slurry on the polishing pad. The reactant distribution component is configured to provide an oxidizer material on the polishing pad to generate a plurality of radicals to react with the article.

Abstract: A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.

Abstract: A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.

Abstract: A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.

Abstract: A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.

Abstract: A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.

Abstract: An integrated circuit and methods for forming the same are provided. The method includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening, wherein the diffusion barrier layer has a top edge substantially level with a top surface of the low-k dielectric layer; filling a metal line in the opening; recessing a top surface of the metal line below a top edge of the diffusion barrier layer to form a recess; and forming a metal cap on the metal line, wherein the metal cap is substantially within the recess.

Abstract: A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.

Abstract: A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.

Abstract: A CMP process for selectively polishing an overlying material layer with an underlying layer comprising at least one material in a semiconductor device fabrication process including providing a semiconductor wafer process surface including a first material layer overlying a second layer including one material; mixing at least two slurry mixtures including a first CMP slurry formulation optimized for removing the first material layer and a second CMP slurry formulation optimized for removing the at least a second layer to form a slurry formulation mixture; and, carrying out a CMP process using the slurry formulation mixture to remove the first material layer and at least a portion of the at least a second layer.

Abstract: A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.

Abstract: A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.

Abstract: A method of adhering a silicate layer to dielectric layer comprising the following steps. A structure having an overlying dielectric layer formed thereover is provided. An adhesion promoter layer is formed upon the dielectric layer. The adhesion promoter layer including adhesion promotion molecules. The dielectric layer and the adhesion promoter layer are treated to a low-temperature treatment to bind at least some of the adhesion promotion molecules to the dielectric layer. A silicate layer is formed upon the low-temperature treated adhesion promoter layer. The silicate layer and the low-temperature treated adhesion promoter layer are treated to a high-temperature treatment to bind at least some of the adhesion promotion molecules to the silicate layer whereby the silicate layer is adhered to the dielectric layer.

Abstract: A CMP process for selectively polishing an overlying material layer with an underlying layer comprising at least one material in a semiconductor device fabrication process including providing a semiconductor wafer process surface including a first material layer overlying a second layer including one material; mixing at least two slurry mixtures including a first CMP slurry formulation optimized for removing the first material layer and a second CMP slurry formulation optimized for removing the at least a second layer to form a slurry formulation mixture; and, carrying out a CMP process using the slurry formulation mixture to remove the first material layer and at least a portion of the at least a second layer.

Abstract: A method of adhering a silicate layer to dielectric layer comprising the following steps. A structure having an overlying dielectric layer formed thereover is provided. An adhesion promoter layer is formed upon the dielectric layer. The adhesion promoter layer including adhesion promotion molecules. The dielectric layer and the adhesion promoter layer are treated to a low-temperature treatment to bind at least some of the adhesion promotion molecules to the dielectric layer. A silicate layer is formed upon the low-temperature treated adhesion promoter layer. The silicate layer and the low-temperature treated adhesion promoter layer are treated to a high-temperature treatment to bind at least some of the adhesion promotion molecules to the silicate layer whereby the silicate layer is adhered to the dielectric layer.

Abstract: A method for removing a metal oxide overlayer over a target polishing surface in conjunction with a chemical mechanical polishing (CMP) process to improve polishing uniformity including providing a substrate target polishing surface having a layer of an oxide of a metal overlying said metal to be chemically mechanically polished; removing the layer of an oxide of the metal using an oxide removal solution prior to performing a CMP process with an abrasive slurry; and, polishing the target polishing surface according to an a CMP process with an abrasive slurry including at least one of an oxidizer and a complexing agent.

Abstract: A bimodal slurry system for a chemical mechanical polishing process including a dispersion comprising a plurality of first particles and a plurality of at least one type of second particles said first particles having a mean particle diameter larger by at least a factor of 3 than a mean particle diameter of the at least one type of second particles said first particles further being compressible.

Abstract: A bimodal slurry system for a chemical mechanical polishing process including a dispersion comprising a plurality of first particles and a plurality of at least one type of second particles said first particles having a mean particle diameter larger by at least a factor of 3 than a mean particle diameter of the at least one type of second particles said first particles further being compressible.

Abstract: Disclosed is a method for treating highly concentrated wastewater by electrolysis and oxidization, said method being characterized in that the electrolysis and oxidization are carried out in a fluidized bed of a suitable particulate carrier. The electrolytic reduction efficiency of ferric ions is improved by the fluidized particulate carrier, and thus a high proportion of iron(III) to iron(II) can be sustained in the system. This invention allows extensive purification of wastewater with improved efficiency.