Abstract: A method for fabricating high-voltage CMOS transistors comprises the steps of: forming a well of a second conductivity type and two lightly-doped diffusion regions of the second conductivity type in a silicon substrate of a first conductivity type; forming a plurality of shielding blocks over the silicon substrate to define source/drain and gate regions; implanting impurities of the first conductivity type in the diffusion regions of the first conductivity type to form drift regions of the first conductivity type therein; implanting impurities of the second conductivity type in the diffusion regions of the second conductivity type to form drift regions of the second conductivity type therein; forming field oxide layers between the shielding blocks over the silicon substrate; removing the shielding blocks; forming gate oxide layers on the exposed surfaces of the silicon substrate and the well respectively; forming gate electrodes over the gate oxide layers; and forming source/drain implanted regions of the fir

Abstract: A method for manufacturing a CMOS transistor of integrated circuits having metal gates and self-aligned source and drain electrodes. The channel length can be precisely defined, and the leakage current can be reduced. Furthermore, the threshold voltage of the transistor can be increased by implanting impurities into the well or the substrate.

Abstract: A method of fabricating a high-voltage metal-gate CMOS device is disclosed. First, a semiconductor substrate of a first conductivity type having a well region of a second conductivity type is provided. Next, a barrier layer is formed and patterned to form openings for prospective source/drain regions. Then, through the openings, low concentrations of impurities of the first conductivity type and the second conductivity type are implanted into the well region and the semiconductor substrate, respectively. After performing a first thermal treatment, lightly doped source/drain regions of the first conductivity type and the second conductivity type are formed respectively, wherein an oxide layer is also formed within the openings. A sidewall spacer is formed on the sidewalls of the openings.

Abstract: A process for fabricating a high-voltage metal-gate CMOS transistor is disclosed. The CMOS transistor comprises a pair of complementary NMOS and PMOS transistors. The CMOS transistor is fabricated on an semiconductor substrate of a first conductivity type, which has a well region of a second conductivity type therein; therefore, the PMOS and NMOS are fabricated onto the substrate or well region, separately. It can be understood that use of the opening prepared in the initial, and, the only primary shielding layer for the location of the source/drain regions of both the NMOS and PMOS transistors, comprises the key to the precision alignment, and to the dimensional symmetry of the transistors fabricated. This is because that the subsequent fabrication procedural steps after the formation of the shielding layer with the set openings, including all the deposition, the ion implantation, and the etching, etc.

Abstract: An improved structure and process of fabricating an electrically erasable programmable read only memory device (EEPROM's) wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide is removed forming a depression in the surface. Impurity ions are implanted in the depression forming a highly doped tunneling region. A tunnel oxide layer is formed on the substrate surface fully covering the tunneling region. Next, the floating gate layer is formed on the tunnel oxide layer. The gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the spaced source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact openings are formed.

Abstract: Reduced-size LDMOS transistor having reduced leakage and a reduced propensity to latch-up. The LDMOS transistor has a trench with vertical sidewalls adjacent to a source region to help reduce a vertical projective area of the source region.

Abstract: A MOSFET semiconductor, erasable programmable ROM device on a lightly doped semiconductor substrate comprising field oxide regions in the semiconductor substrate. The field oxide regions extends down into sunken regions in the substrate through the openings. At least one of the field oxide regions is removed from the substrate to provide an opened one of the sunken regions in the substrate below the removed one of the field oxide regions. Ion implanted regions lie in the substrate below the openings. A gate oxide layer over the opened sunken region, and a floating gate over the gate oxide layer. Preferably, a tunnel oxide region is formed on the surface of the device with the floating gate overlying the tunnel oxide region to form an EEPROM device. The exposed sunken region has a V-shaped cross section sunken region extending deep into the substrate.

Abstract: A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided.

Abstract: A process of fabricating a bipolar junction transistor forms, on the substrate, a masking layer including an opening, an intermediate masking portion surrounded by the opening and an outer masking portion. The masking layer consists of a pad oxide and a silicon nitride. A photoresist is then formed on the outer masking portion. A first ion implantation process at a relatively low dose and a relatively high energy is performed to form a base region underlying the intermediate masking portion, and a second ion implantation process at a relatively high dose and a relatively low energy is performed to form a base contact region underlying the opening. Then, the photoresist is removed. A field oxide is grown in the opening of the masking layer, followed by removing the masking layer.

Abstract: A process for fabricating metal-gate CMOS transistors on a semiconductor substrate having a well region therein is disclosed herein. The process comprises the steps of: First forming a shielding layer with designated patterns on the substrate and the well region, and, then, forming first field oxides on the substrate or the well region between the designated patterns of the shielding layer through a thermal oxidation procedure. After that, the first field oxides are removed to expose recesses, and drift regions are formed in the substrate and the well region beneath the recesses. Next, second field oxides are formed above the recesses and the shielding layer are subsequently removed. Then, heavily-doped regions are formed in the substrate and the well region between the drift regions, and lightly-doped regions are formed beneath the heavily-doped region, both of which serve as source/drain regions.

Abstract: A method for fabricating a bipolar power transistor is disclosed, wherein the bipolar power transistor is made on a first type of heavily doped substrate.

Abstract: A process for fabricating a bipolar junction transistor by forming a trench in a silicon substrate. A lightly-doped base region is formed adjacent to the sidewalls of the trench, and a heavily-doped base region is formed under the bottom of the trench. Silicon oxide layers are formed along the sidewalls and bottom of the trench with a contact window provided to expose part of the lightly-doped base region. A polysilicon layer is formed in the trench, and is heavily doped by a dopant which in turn diffuses into the lightly-doped base region through the contact window to form an emitter region. A collector region is formed in the upper surface of the lightly-doped base region.

Abstract: A method of producing a reduced-size LDMOS transistor having reduced leakage and latch-up possibility by reducing the vertical projective area of the source electrodes of the LDMOS transistor, which is done by forming first trenches to reach a substrate of the LDMOS transistor.

Abstract: A process for fabricating lateral bipolar junction transistor semiconductor device. Base and emitter regions are precisely aligned. The resulting lateral width of the base region of the transistor device is able be precisely controlled. A heavily-doped implantation region is formed underneath the base region of the transistor structural configuration such that electron carriers in the transistor are prevented from escaping from beneath the base region of the transistor.

Abstract: Reduced-size VDMOS transistor having reduced leakage and a reduced propensity to latch-up. The VDMOS transistor has a reduced vertical projective area of the source region.

Abstract: A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made via a self-alignment technique. The collector region of the transistor is contacted through the floor of the trench while the base region of the transistor is contacted in a region that surrounds the trench. The described method is compatible with the simultaneous manufacture of FET devices on the same chip.

Abstract: The present invention relates to a method of forming a double diffused metal-oxide-semiconductor (DMOS) transistor which enables the formation of short channels. This method uses silicon nitride sidewall spacers so that the sidewall spacers can be removed without etching the field oxide, therefore the length of the channel can be minimized to reduce the channel resistance.

Abstract: A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor's implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.

Abstract: A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor's implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.

Abstract: An improved structure and process of fabricating a programmable and erasable read only memory device wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide region is removed forming a depression in the surface. Impurity ions are implanted into the depression forming a lightly doped source region. A tunnel oxide layer is formed on the substrate surface. Next, the floating gate layer is formed on the tunnel oxide layer which at least partially overlies the lightly doped source region. A gate insulation layer and control gate layer are formed over the floating gate layer. Subsequently, the source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact opening are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and control gate to form an electrical programmable memory device.