Abstract: A process for fabricating a high-voltage semiconductor power device on a substrate of a first conductivity type is described. A lightly-doped epitaxial layer of the first conductivity type having a first thickness and a doped layer of a second conductivity type having a second thickness are then formed on the substrate. First grooves are formed by etching through the doped layer into the lightly-doped epitaxial layer. A pad oxide layer is formed on the exposed surfaces of the lightly-doped epitaxial layer and the doped layer. Silicon nitride spacers are formed on sidewalls of the first grooves. The thickness of portions of the pad oxide layer not covered by the silicon nitride spacers is increased by thermal oxidation. The silicon nitride spacers and portions of the pad oxide layer underlying the silicon nitride spacers are then removed.

Abstract: A method for fabricating a junction terminal extension structure for a high-voltage integrated circuit device. The method provides for the formation of two silicon oxide layers having a two-stage shaped final field region oxide in the proximity of the anode of a high-voltage integrated circuit device. A field region anode flat plate can be formed in the area of the two-stage shaped structure. The distance between the edge of the field region flat plate and the surface of the silicon substrate thus be increased to compared to prior art structures, and the electric field intensity therebetween can therefore be reduced, resulting in the increased breakdown voltage to increase the reliability of the integrated circuit device.

Abstract: A method of producing reduced-size VDMOS transistors having reduced leakage and a reduced propensity to latch-up. These advantages are attained by reducing the vertical projective area of the source electrodes of the VDMOS transistors. This is done by forming first trenches which are sufficiently deep to reach an epitaxial layer on a substrate of the VDMOS transistors before second trenches are formed.

Abstract: A semiconductor CMOS device on a silicon substrate doped with an N- dopant is manufactured by a process of forming a mask upon the substrate, forming field oxide structures upon the substrate through the mask, removing the mask, forming a sacrificial layer on the surface of the substrate between the field oxide structures, forming a P-well mask on the substrate for the NMOS portion of the device, implanting dopant ions to form an NMOS retrograde P-well through the P-well mask, performing an NMOS V.sub.T first implant of ions through the P-well mask into selected regions of the the substrate, performing a second V.sub.T implant of ions into the substrate, performing a PMOS punchthrough voltage implant of ions into the substrate, forming doped polysilicon gate structures, and forming doped source/drain regions.

Abstract: A method of fabrication of an semiconductor device comprises applying an impurity of a predetermined polarity to a silicon substrate; forming a well by applying an impurity of an opposite polarity to a region in the silicon substrate; forming a first masking layer on the surface of the substrate; providing openings in the masking layer and implanting dopant ions of a first polarity into the surface of the substrate in a set of first regions selected in the substrate and the well forming a second masking layer on the surface of the substrate; implanting dopant ions of a second polarity through a second mask in other regions selected in the well and the substrate; removal of the second masking layer; formation of field oxide structures over the first and second regions; forming gate oxide layers above the exposed portions of the first and second central regions; and formation of conductive gate structures over the gate oxide layers.

Abstract: A method for manufacturing CMOS transistors for integrated circuits which have metal gates and heavily doped source and drain electrode regions, thereby improving their resisting capability to a high voltage while reducing cycle time for manufacture. As a result, the performance of the transistors is improved and the cost of manufacture is reduced.

Abstract: An improved structure and process of fabricating an electrically erasable programmable read only memory device (EEPROM's) wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide is removed forming a depression in the surface. Impurity ions are implanted in the depression forming a highly doped tunneling region. A tunnel oxide layer is formed on the substrate surface fully covering the tunneling region. Next, the floating gate layer is formed on the tunnel oxide layer. The gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the spaced source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact openings are formed.

Abstract: The present invention discloses a method for manufacturing lateral bipolar transistors of integrated circuits which have expanded collector regions, thereby raising the gain of the lateral bipolar transistors while reducing cycle time for manufacture. As a result, the performance of the transistors is improved and the cost of manufacture is reduced.