Abstract: A biological particle capturing and retrieving system includes a capturing device including a substrate, an isolating layer and a driving unit, and a retrieving device including a micropipette. The isolating layer includes a top surface, multiple pores, and multiple fluidic grooves indented from the top surface, arranged in a herringbone pattern, and each having a bottom surface. The pores are formed in the bottom surfaces of the fluidic grooves, and each capture a biological particle in a liquid sample. The driving unit drives the liquid sample to flow by electrowetting through the pores. The micropipette has a carrier coated with a biological particle-binding material binding with the biological particle received in a corresponding pore.

Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Abstract: A signal modulation method, an adaptive equalizer and a memory storage device are provided. The method includes: receiving a first signal; performing a first modulation on the first signal based on a first power mode to generate a second signal having a first eye-width; performing a second modulation based on a second power mode to generate the second signal having a second eye-width; determining whether the first eye-width and the second eye-width meet a first condition; if yes, performing a third modulation based on the first power mode to generate the second signal having a third eye-width; otherwise, performing the third modulation based on the second power mode to generate the second signal having the third eye-width. Therein, a power consumption of performing the second modulation is less than that of performing the first modulation. Therefore, an efficiency of the adaptive equalizer may be improved.

Abstract: A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating a sensing voltage pair according to the differential signal, where the sensing voltage pair includes a first sensing voltage and a second sensing voltage, a voltage value of the first sensing voltage is related to a first differential signal of the differential signal, and a voltage value of the second sensing voltage is related to a second differential signal of the differential signal; and receiving the sensing voltage pair and outputting a sampling data stream according to a clock of the differential signal and a voltage relative relationship of the sensing voltage pair.

Abstract: A device includes a semiconductor substrate, which has a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A first and a second grid line are parallel to each other, and are disposed on the backside of, and overlying, the semiconductor substrate. A stacked layer includes an adhesion layer, a metal layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.

Abstract: A substrate is provided. The substrate has a source/drain region formed therein and a dielectric layer formed thereover. A contact hole is etched in the dielectric layer to expose a portion of the source/drain region. A metal material is formed on the source/drain region exposed by the opening. A first annealing process is performed to facilitate a reaction between the metal material and the portion of the source/drain region disposed therebelow, thereby forming a metal silicide in the substrate. The first annealing process is a spike annealing process. A remaining portion of the metal material is removed after the performing of the first annealing process. Thereafter, a second annealing process is performed. Thereafter, a contact is formed in the contact hole, the contact being formed on the metal silicide.

Abstract: A device includes a semiconductor substrate, which has a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A first and a second grid line are parallel to each other, and are disposed on the backside of, and overlying, the semiconductor substrate. A stacked layer includes an adhesion layer, a metal layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.

Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Abstract: A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.

Abstract: A light emitting diode (LED) module and a display device adopting the same LED module are provided. The LED module includes a circuit substrate, a LED chip, a connector and a conductive line. The LED chip has at least three pins, and the LED chip is fixed on the circuit substrate through the pins, wherein one of the pins is defined as a no connection (NC) pin. The connector includes a non-conductive housing, at least one fixing pin and a conductor. The fixing pin is connected to the non-conductive housing, and the non-conductive housing is fixed on the circuit substrate through the said at least one fixing pin. A part of the non-conductive housing is covered with the conductor. The conductive line is disposed on the circuit substrate and is electrically connected between the conductor and the NC pin.

Abstract: A back-light module including a light guide plate (LGP), first light-emitting devices, and second light-emitting devices is provided. The LGP has a top-emitting surface, a bottom surface and a side surface. The LGP has at least one indentation. The indentation has a first light-incident sidewall and a pair of second light-incident sidewalls. The second light-incident sidewalls are located on two sides of the first light-incident sidewall and adjacent to the first light-incident sidewall. Normal vectors of the second light-incident sidewalls and the first light-incident sidewall are not parallel. The first light-emitting devices are located in the indentation, and a first light beam propagating toward the first light-incident sidewall is emitted from each of the first light-emitting devices. The second light-emitting devices are located in the indentation, and a second light beam propagating toward one of the second light-incident sidewalls is emitted from each of the second light-emitting devices.

Abstract: A device includes a semiconductor substrate, which has a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A first and a second grid line are parallel to each other, and are disposed on the backside of, and overlying, the semiconductor substrate. A stacked layer includes an adhesion layer, a metal layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines.

Abstract: A back-light module including a light guide plate (LGP), first light-emitting devices, and second light-emitting devices is provided. The LGP has a top-emitting surface, a bottom surface and a side surface. The LGP has at least one indentation. The indentation has a first light-incident sidewall and a pair of second light-incident sidewalls. The second light-incident sidewalls are located on two sides of the first light-incident sidewall and adjacent to the first light-incident sidewall. Normal vectors of the second light-incident sidewalls and the first light-incident sidewall are not parallel. The first light-emitting devices are located in the indentation, and a first light beam propagating toward the first light-incident sidewall is emitted from each of the first light-emitting devices. The second light-emitting devices are located in the indentation, and a second light beam propagating toward one of the second light-incident sidewalls is emitted from each of the second light-emitting devices.

Abstract: A light emitting diode (LED) module and a display device adopting the same LED module are provided. The LED module includes a circuit substrate, a LED chip, a connector and a conductive line. The LED chip has at least three pins, and the LED chip is fixed on the circuit substrate through the pins, wherein one of the pins is defined as a no connection (NC) pin. The connector includes a non-conductive housing, at least one fixing pin and a conductor. The fixing pin is connected to the non-conductive housing, and the non-conductive housing is fixed on the circuit substrate through the said at least one fixing pin. A part of the non-conductive housing is covered with the conductor. The conductive line is disposed on the circuit substrate and is electrically connected between the conductor and the NC pin.

Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.

Abstract: A novel surface acoustic wave device with a decreased velocity dispersion and a low insertion loss as well as the fabrication method therefore is provided. The surface acoustic wave device includes a substrate, an insulating layer with an indentation on the substrate, a silicon layer divided by an etched window with a first portion on the insulating layer and a second portion suspended above the indentation, a piezoelectric layer on the first and the second portions of the silicon layer, and at least an electrode on the piezoelectric layer.

Abstract: A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.

Abstract: A communication module with dual systems for processing a first RF signal and a second RF signal that belong to different communication systems is provided. The communication module includes a first connection port and a signal distribution circuit. The first connection port is coupled to an external circuit, and the signal distribution circuit is coupled to the first connection port and between a first system path and a second system path inside the communication module. Regardless whether the external circuit is composed by an dual-band antenna or two uni-band antenna, the signal distribution circuit controls the first RF signal transmitting along the path between the first connection port and the first system path and controls the second RF signal transmitting along the path between the path between the first connection port and the second system path.

Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.