Abstract: A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.

Abstract: A communication module with dual systems for processing a first RF signal and a second RF signal that belong to different communication systems is provided. The communication module includes a first connection port and a signal distribution circuit. The first connection port is coupled to an external circuit, and the signal distribution circuit is coupled to the first connection port and between a first system path and a second system path inside the communication module. Regardless whether the external circuit is composed by an dual-band antenna or two uni-band antenna, the signal distribution circuit controls the first RF signal transmitting along the path between the first connection port and the first system path and controls the second RF signal transmitting along the path between the path between the first connection port and the second system path.

Abstract: A communication transmission system is applied to an application device and includes a power detection circuit, and a radio frequency module. The power detection circuit is used for detecting the power on the output port of the communication transmission system, and for producing a feedback signal. The radio frequency module is connected to the power detection circuit for receiving the feedback signal so as to adjust its output power. In addition, the power detection circuit is built to be independent of the RF module for directly detecting the power on the output port of the communication transmission system which represents the actual power of the application device, thereby achieving the purpose of outputting a more stable and accurate output power through the RF module.

Abstract: A testing system for a RF module includes a metal casing formed a testing space therein, a RF testing socket disposed inside the testing module, and a pressing manipulator penetrating through the metal casing. A shielding material layer is disposed on the internal surface of the metal casing so that the RF signal is isolated inside the metal casing. An end of the pressing manipulator extends into the testing space. The pressing manipulator is controlled automatically and provides for a pressure on a RF module disposed on the testing module so as to execute a testing process. As mentioned above, the testing set for a RF module can prevent from RF testing interference and the testing manufacture efficiency is improved.

Abstract: A conductive metal structure applied to a module IC includes a wafer, a first insulating unit, and a first conductive unit. The wafer has a main body and a through hole passing through the main body. The first insulating unit has a first inner insulating layer formed on an inner surface of the through hole and a first outer insulating layer that is extended from the first inner insulating layer and is formed on a first bottom surface of the main body. The first conductive unit has a first inner conductive layer formed on the first inner insulating layer and at least one first conductive pad formed on the first outer insulating layer. The present invention integrates semiconductor technologies of etching and deposition and combines them with the development of the module IC in order to provide a conductive metal structure that has lower cost and is manufactured easily.

Abstract: A novel surface acoustic wave device with a decreased velocity dispersion and a low insertion loss as well as the fabrication method therefor is provided. The surface acoustic wave device includes a substrate, an insulating layer with an indentation on the substrate, a silicon layer with a first portion on the insulating layer and a second portion suspended above the indentation, a piezoelectric layer on the first and the second portions of the silicon layer, and at least an electrode on the piezoelectric layer.

Abstract: A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.

Abstract: A novel surface acoustic wave device with a decreased velocity dispersion and a low insertion loss as well as the fabrication method therefor is provided. The surface acoustic wave device includes a substrate, an insulating layer with an indentation on the substrate, a silicon layer with a first portion on the insulating layer and a second portion suspended above the indentation, a piezoelectric layer on the first and the second portions of the silicon layer, and at least an electrode on the piezoelectric layer.

Abstract: Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device comprises the low-k dielectric layer overlying an etch stop layer overlying a substrate, and a conductive material embedded in the dielectric layer and the etch stop layer, electrically connecting to the substrate.

Abstract: An apparatus and method for controlling a rotation speed of a fan. A comparator is used to detect an analog signal driving the fan. When the analog signal is detected abnormal, a voltage generation circuit generates a particular voltage to maintain a lowest operation voltage of the fan. A protection circuit is provided to let the fan driven by the analog signal again by means of receiving a signal from a system the fan is disposed at when the analog signal becomes normal.

Abstract: A method for plasma cleaning a CVD reactor chamber including providing a plasma enhanced CVD reactor chamber comprising residual deposited material; performing a first plasma process comprising an oxygen containing plasma; performing a second plasma process comprising an argon containing plasma; and, performing a third plasma process comprising a fluorine containing plasma.

Abstract: A novel surface acoustic wave device with a decreased velocity dispersion and a low insertion loss as well as the fabrication method therefor is provided. The surface acoustic wave device includes a substrate, an insulating layer with an indentation on the substrate, a silicon layer with a first portion on the insulating layer and a second portion suspended above the indentation, a piezoelectric layer on the first and the second portions of the silicon layer, and at least an electrode on the piezoelectric layer.

Abstract: An improved damascene process for fabricating a semiconductor device. A dielectric layer comprising at least both fluorine and nitrogen is formed overlying a substrate, in which a nitrogen content in the dielectric layer is about 5% to 10%. The dielectric layer is subsequently pattered to form at least one damascene opening therein. A metal layer is formed overlying the dielectric layer and fills the damascene opening. The excess metal layer on the dielectric layer is removed to leave the metal layer in the damascene opening. A semiconductor device with the same damascene structure is also disclosed.

Abstract: A method and system for reducing wafer edge residue following a chemical mechanical polishing operation. A semiconductor wafer can be polished utilizing a chemical mechanical polishing apparatus. Thereafter, an acid etch operation may be performed to remove a residue, such as tungsten (W), collected on the semiconductor wafer as a result of the chemical mechanical polishing operation. A spin etch operation removes residue from the edges of the semiconductor wafer following chemical mechanical polishing of the semiconductor wafer.

Abstract: A thin film layered surface acoustic wave device includes a substrate, a GaN piezoelectric film, an AlN piezoelectric film and interdigital transducer electrodes. The GaN piezoelectric film is deposited on the substrate by chemical vapor deposition (CVD) or physical vapor deposition (PVD) method. Then the AlN piezoelectric film is deposited on top surface of the GaN piezoelectric film by the same way. Finally, the interdigital transducer electrodes are deposited on top surface of AlN piezoelectric film and form by etching of lift off method. Accordingly, high operating frequency and low loss surface acoustic wave devices can be produced which can be integrated with high frequency devices, such as HBT and HEMT, and different devices.

Abstract: A method suitable for cleaning the interior surfaces of a process chamber is disclosed. The invention is particularly effective in removing silicon nitride and silicon dioxide residues from the interior surfaces of a chemical vapor deposition (CVD) chamber. The method includes reacting nitrous oxide (N2O) gas with nitrogen trifluoride (NF3) gas in a plasma to generate nitric oxide (NO) and fluoride (F) radicals. Due to the increased density of nitric oxide radicals generated from the nitrous oxide, the etch and removal rate of the residues on the interior surfaces of the chamber is enhanced. Consequently, the quantity of nitrogen trifluoride necessary to efficiently and expeditiously carry out the chamber cleaning process is reduced.

Abstract: A method for plasma cleaning a CVD reactor chamber including providing a plasma enhanced CVD reactor chamber comprising residual deposited material; performing a first plasma process comprising an oxygen containing plasma; performing a second plasma process comprising an argon containing plasma; and, performing a third plasma process comprising a fluorine containing plasma.

Abstract: A method and system for reducing wafer edge residue following a chemical mechanical polishing operation. A semiconductor wafer can be polished utilizing a chemical mechanical polishing apparatus. Thereafter, an acid etch operation may be performed to remove a residue, such as tungsten (W), collected on the semiconductor wafer as a result of the chemical mechanical polishing operation. A spin etch operation removes residue from the edges of the semiconductor wafer following chemical mechanical polishing of the semiconductor wafer.

Abstract: A inter-metal dielectric layer structure and the method of the same are provided. The method includes the following steps. A process gas is introduced to form a low-k dielectric layer over the substrate. A reactant gas is in situ introduced to etch the low-k dielectric layer back and to react with the process gas to form a dielectric layer containing an extra element on the low-k dielectric layer. The extra element is provided by the reactant gas. A volume ratio of the reactant gas to the process gas is larger than about 2. The reactant gas may be a nitrogen fluoride (NF3) gas for providing extra nitrogen (N) or a carbon fluoride (CxFy) gas for providing extra carbon (C).

Abstract: A method and system for reducing wafer edge residue following a chemical mechanical polishing operation. A semiconductor wafer can be polished utilizing a chemical mechanical polishing apparatus. Thereafter, an acid etch operation may be performed to remove a residue, such as tungsten (W), collected on the semiconductor wafer as a result of the chemical mechanical polishing operation. A spin etch operation removes residue from the edges of the semiconductor wafer following chemical mechanical polishing of the semiconductor wafer.