Patents by Inventor Shenqing Fang
Shenqing Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11450680Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.Type: GrantFiled: September 8, 2020Date of Patent: September 20, 2022Assignee: Infineon Technologies LLCInventors: Chun Chen, Mark Ramsbey, Shenqing Fang
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Patent number: 11342429Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: GrantFiled: September 30, 2020Date of Patent: May 24, 2022Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad, James Pak
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Patent number: 11257675Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.Type: GrantFiled: June 26, 2019Date of Patent: February 22, 2022Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Timothy Thurgate, Kuo Tung Chang
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Publication number: 20220005933Abstract: A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.Type: ApplicationFiled: July 15, 2021Publication date: January 6, 2022Inventors: Yi Ma, Shenqing Fang, Robert Ogle
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Patent number: 11069789Abstract: A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.Type: GrantFiled: May 4, 2020Date of Patent: July 20, 2021Assignee: MONTEREY RESEARCH, LLCInventors: Yi Ma, Shenqing Fang, Robert Ogle
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Patent number: 11069699Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: GrantFiled: August 3, 2020Date of Patent: July 20, 2021Assignee: Cypress Semiconductor CorporationInventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. Van Buskirk
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Publication number: 20210210610Abstract: Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device.Type: ApplicationFiled: February 17, 2021Publication date: July 8, 2021Applicant: Cypress Semiconductor CorporationInventors: Angela Tai Hui, Scott Bell, Shenqing Fang
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Publication number: 20210134715Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend tit rough the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.Type: ApplicationFiled: November 9, 2020Publication date: May 6, 2021Inventors: Shenqing Fang, Connie Pin-Chin Wang, Wen Yu, Fei Wang
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Publication number: 20210104533Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.Type: ApplicationFiled: September 8, 2020Publication date: April 8, 2021Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Mark Ramsbey, Shenqing Fang
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Publication number: 20210091198Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: ApplicationFiled: September 30, 2020Publication date: March 25, 2021Applicant: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon KIM, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. HADDAD, James Pak
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Publication number: 20210082927Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: ApplicationFiled: August 3, 2020Publication date: March 18, 2021Applicant: Cypress Semiconductor CorporationInventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. VAN BUSKIRK
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Patent number: 10923601Abstract: A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.Type: GrantFiled: April 10, 2018Date of Patent: February 16, 2021Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Shenqing Fang, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad
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Publication number: 20200365709Abstract: A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.Type: ApplicationFiled: May 4, 2020Publication date: November 19, 2020Inventors: Yi Ma, Shenqing Fang, Robert Ogle
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Patent number: 10833013Abstract: At integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.Type: GrantFiled: November 7, 2019Date of Patent: November 10, 2020Assignee: Monterey Research, LLCInventors: Shenqing Fang, Connie Pin-Chin Wang, Wen Yu, Fei Wang
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Patent number: 10833009Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.Type: GrantFiled: September 28, 2018Date of Patent: November 10, 2020Assignee: Monterey Research, LLCInventors: Shenqing Fang, Connie Pin-Chin Wang, Wen Yu, Fei Wang
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Patent number: 10818761Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.Type: GrantFiled: July 19, 2019Date of Patent: October 27, 2020Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
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Patent number: 10777568Abstract: A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.Type: GrantFiled: February 10, 2017Date of Patent: September 15, 2020Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Mark Ramsbey, Shenqing Fang
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Patent number: 10756101Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: GrantFiled: January 20, 2020Date of Patent: August 25, 2020Assignee: Cypress Semiconductor CorporationInventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. Van Buskirk
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Patent number: 10686044Abstract: A memory device that has a first gate disposed adjacent to a second gate and a first dielectric structure disposed between the first and second gates. The first dielectric structure has at least four layers of oxide and nitride films arranged in an alternating layer, in which each of the at least four or more layers includes a width in an approximate range of 30 ? or less. The first dielectric structure further includes a top surface that is substantially un-etched.Type: GrantFiled: December 19, 2018Date of Patent: June 16, 2020Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Shenqing Fang
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Publication number: 20200168618Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: ApplicationFiled: January 20, 2020Publication date: May 28, 2020Applicant: Cypress Semiconductor CorporationInventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. VAN BUSKIRK