Patents by Inventor Shenqing Fang

Shenqing Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits with non-volatile memory and methods for manufacture
    Patent number: 8836006
    Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Spansion LLC
    Inventors: Kuo Tung Chang, Chun Chen, Shenqing Fang
  • Method to improve charge trap flash memory core cell performance and reliability
    Patent number: 8835277
    Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Spansion LLC
    Inventors: Tung-Sheng Chen, Shenqing Fang
  • High voltage gate formation
    Patent number: 8822289
    Abstract: Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 2, 2014
    Assignee: Spansion LLC
    Inventors: Shenqing Fang, Chun Chen
  • Process charging protection for split gate charge trapping flash
    Patent number: 8816438
    Abstract: A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Spansion LLC
    Inventors: Chun Chen, Sameer Haddad, Kuo Tung Chang, Mark Ramsbey, Unsoon Kim, Shenqing Fang
  • Memory cell system with multiple nitride layers
    Patent number: 8809936
    Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 19, 2014
    Assignees: Globalfoundries Inc., Spansion LLC
    Inventors: Lei Xue, Rinji Sugino, YouSeok Suh, Hidehiko Shiraiwa, Meng Ding, Shenqing Fang, Joong Jeon
  • Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions
    Publication number: 20140210012
    Abstract: Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing FANG, Unsoon Kim
  • Non-volatile FINFET memory device and manufacturing method thereof
    Patent number: 8785275
    Abstract: Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 22, 2014
    Assignee: Spansion LLC
    Inventors: Chun Chen, Shenqing Fang
  • Process Charging Protection for Split Gate Charge Trapping Flash
    Publication number: 20140167135
    Abstract: A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Chun CHEN, Sameer Haddad, Kuo Tung Chang, Mark Ramsbey, Unsoon Kim, Shenqing Fang
  • Charge Trapping Split Gate Embedded Flash Memory and Associated Methods
    Publication number: 20140167141
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Mark RAMSBEY, Chun CHEN, Sameer HADDAD, Kuo Tung CHANG, Unsoon KIM, Shenqing FANG, Yu SUN, Calvin GABRIEL
  • Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells
    Publication number: 20140167142
    Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Chun Chen, Mark Ramsbey, Shenqing Fang
  • Charge Trapping Split Gate Device and Method of Fabricating Same
    Publication number: 20140170843
    Abstract: Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Chun CHEN, Shenqing FANG, Unsoon KIM, Mark RAMSBEY, Kuo Tung CHANG, Sameer HADDAD
  • Memory Gate Landing Pad Made From Dummy Features
    Publication number: 20140167128
    Abstract: Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Mark RAMSBEY, Chun Chen, Unsoon Kim, Shenqing Fang
  • THREE DIMENSIONAL CAPACITOR
    Publication number: 20140167220
    Abstract: Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Mark RAMSBEY, Unsoon KIM, Shenqing FANG, Chun CHEN, Kuo Tung CHANG
  • High Voltage Gate Formation
    Publication number: 20140167137
    Abstract: Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing FANG, Chun CHEN
  • Memory First Process Flow and Device
    Publication number: 20140167140
    Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing FANG, Chun CHEN, Unsoon KIM, Mark RAMSBEY, Kuo Tung CHANG, Sameer HADDAD, James PAK
  • Integrated Circuits With Non-Volatile Memory and Methods for Manufacture
    Publication number: 20140167139
    Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Spansion LLC
    Inventors: Kuo Tung CHANG, Chun CHEN, Shenqing FANG
  • Memory Device Interconnects and Method of Manufacture
    Publication number: 20140151887
    Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 5, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing Fang, Connie WANG, Wen Yu, Fei Wang
  • Sonos memory cells having non-uniform tunnel oxide and methods for fabricating same
    Patent number: 8742496
    Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: June 3, 2014
    Assignee: Spansion LLC
    Inventors: Shenqing Fang, Gang Xue, Wenmei Li, Inkuk Kang
  • Memory Device Interconnects and Method of Manufacture
    Publication number: 20140145337
    Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines extend through the first inter-level dielectric layer. Each of a plurality of source line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines. Each of the plurality of staggered bit line contacts extend through the first and second inter-level dielectric layes to respective bit lines.
    Type: Application
    Filed: December 10, 2013
    Publication date: May 29, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing Fang, Connie WANG, Wen Yu, Fei Wang
  • NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20140148001
    Abstract: Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: Spansion LLC
    Inventors: Chun CHEN, Shenqing Fang