Patents by Inventor Shigekazu Komatsu

Shigekazu Komatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150638
    Abstract: It is an object of the present invention to provide a thermally conductive sheet that is excellent in thermally conductive property, has insulation property, has a low permittivity, and is excellent in designability. The thermally conductive sheet 1 comprises a binder component 11, titanium oxide, titanium nitride, and a thermally conductive filler 12 other than these, and a ratio of the titanium oxide to the total of the titanium oxide and the titanium nitride is 20 to 90% by mass. An L* value of a surface of the thermally conductive sheet 1 in the L*a*b* color system is preferably 41 or less. The total content of the titanium oxide and the titanium nitride is preferably 0.3 to 10.0 parts by mass based on the total amount 100 parts by mass of the thermally conductive filler 12.
    Type: Application
    Filed: March 11, 2022
    Publication date: May 9, 2024
    Inventors: Yuusuke HARUNA, Hiroshi TAJIMA, Shigekazu UMEMURA, Kanoe KOMATSU, Yuu IIHARA, Junichi KINOSHITA, Kiyoshi IWAI
  • Publication number: 20240019487
    Abstract: A wafer inspection system is provided. The wafer inspection system includes: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Application
    Filed: August 9, 2023
    Publication date: January 18, 2024
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 11762012
    Abstract: A wafer inspection system is provided. The wafer inspection system includes: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: September 19, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Publication number: 20230134360
    Abstract: A wafer inspection system is provided. The wafer inspection system includes: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 4, 2023
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 11567123
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: January 31, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 11061071
    Abstract: A wafer inspection system is provided. The wafer inspection system includes: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 13, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Publication number: 20210190861
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Application
    Filed: March 10, 2021
    Publication date: June 24, 2021
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 10976364
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: April 13, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Publication number: 20200400743
    Abstract: A wafer inspection system is provided. The wafer inspection system includes: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Publication number: 20200348358
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 10753972
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 25, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Publication number: 20200064400
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Publication number: 20170234924
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 9671459
    Abstract: A maintenance carriage of a wafer inspection apparatus can easily unload a test head. A wafer inspection apparatus 10 includes a cell tower 12 in which cells 11 are arranged at four levels, and each of the cells 11 accommodates a test head 15. At an outside of the cell tower 12, a maintenance carriage 27 is arranged. The maintenance carriage 27 includes a carriage base 29 configured to be moved through rollers 28; a test head case 31 configured to accommodate the test head 15; a lift device 30 provided uprightly from the carriage base 29 and configured to move up and down the test head case 31; and a horizontal position adjusting stage 35 provided between a lifter 34 of the lift device 30 and the test head case 31 and configured to move the test head case 31 horizontally with respect to the lifter 34.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: June 6, 2017
    Assignees: TOKYO ELECTRON LIMITED, NIPPO PRECISION CO., LTD
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Publication number: 20150145540
    Abstract: Provided are a semiconductor inspection system and a method for preventing condensation at an interface part. The inspection system is characterized by being equipped with: a probe apparatus configured to bring a probe into contact with a target object whose temperature is controlled so that the probe is electrically connected with the target object; a tester configured to inspect the target object by supplying an inspection signal to the target object and detect an output signal outputted from the target object; an interface part which electrically connects the probe with the tester; a vacuum seal mechanism configured to seal the interface part in an airtight state; a gas exhaust unit configured to evacuate the interior of the interface part to a depressurized atmosphere; and a dry gas supply unit configured to supply a dry gas into the evacuated interface part while controlling a flow rate of the dry gas.
    Type: Application
    Filed: June 18, 2013
    Publication date: May 28, 2015
    Inventors: Shigekazu Komatsu, Takaaki Hoshino
  • Publication number: 20150115991
    Abstract: A maintenance carriage of a wafer inspection apparatus can easily unload a test head. A wafer inspection apparatus 10 includes a cell tower 12 in which cells 11 are arranged at four levels, and each of the cells 11 accommodates a test head 15. At an outside of the cell tower 12, a maintenance carriage 27 is arranged. The maintenance carriage 27 includes a carriage base 29 configured to be moved through rollers 28; a test head case 31 configured to accommodate the test head 15; a lift device 30 provided uprightly from the carriage base 29 and configured to move up and down the test head case 31; and a horizontal position adjusting stage 35 provided between a lifter 34 of the lift device 30 and the test head case 31 and configured to move the test head case 31 horizontally with respect to the lifter 34.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 8766658
    Abstract: A probe includes a contact member brought into contact with an object to be tested. Contact particles having conductivity are uniformly distributed in the contact member. A part of the contact particles protrude from a surface of the contact member on the side of the object to be tested. A conductive member having elasticity is placed on a surface of the contact member on the opposite side to the object to be tested. The probe further includes an insulating sheet including a through hole and the contact member is so positioned as to penetrate the through hole. An upper part of the contact member is formed of a conductor which does not include the contact particles. An additional conductor is placed on a surface of the conductor on the side opposite to the object to be tested.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: July 1, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Shigekazu Komatsu
  • Patent number: 8723544
    Abstract: A probe card installed in a probe device includes a supporting plate capable of supporting a contact body and a circuit board installed above a top surface of the supporting plate. A connection member is installed at a top surface of the circuit board and the supporting plate and the connection member are connected to each other by a connection body. Load control members are installed at a top surface of the connection member and capable of maintaining a contact load between the contact body and an object to be inspected at a constant level. Elastic members are installed at a peripheral portion of the connection member and capable of fixing a horizontal position of the supporting plate. An intermediate member is installed between the circuit board and the supporting plate and configured to elastically and electrically connect the circuit board and the supporting plate.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: May 13, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shigekazu Komatsu, Syuichi Tsukada
  • Patent number: 8468690
    Abstract: A holding member for use in a test includes a base made of silicon or glass and chips in which devices are formed is mountable thereon. Positioning members made of resist sheets are formed on the top surface of the base. A resist film is formed on the bottom surface of the base, and suction grooves (intersection portions, connection portions) and support members are formed in the resist film. Suction holes are formed in regions of the top surface of the base where the chips are mounted, wherein the suction holes are formed through the base and communicate with the suction groove.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: June 25, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Yasunori Kumagai, Shigekazu Komatsu
  • Patent number: 8471585
    Abstract: A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: June 25, 2013
    Assignees: Tokyo Electron Limited, Fuji Electric Systems Co., Ltd.
    Inventors: Mitsuyoshi Miyazono, Shigekazu Komatsu, Dai Shinozaki, Masahiro Kato, Atsushi Yoshida