Patents by Inventor Shigeki Kobayashi

Shigeki Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140061567
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type.
    Type: Application
    Filed: March 21, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Takeshi Yamaguchi, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu
  • Publication number: 20140061578
    Abstract: A nonvolatile semiconductor memory device below comprises: a memory cell array configured having memory cells arranged therein disposed at intersections of a plurality of first lines and a plurality of second lines formed so as to intersect each other, and the memory cells each comprising a variable resistance element; and a control circuit configured to select and drive the first lines and the second lines. The variable resistance element is configured by a transition metal oxide film. The variable resistance element is electrically connected to a first electrode configured from a metal at a first surface and is electrically connected to a second electrode at a second surface which is on an opposite side to the first surface. A first insulating film is formed between the first electrode and the variable resistance element. The first insulating film is formed by a first material that is formed by covalent binding.
    Type: Application
    Filed: February 28, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki KOBAYASHI, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20140063911
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory layers; and a control unit configured to control a voltage applied to the memory cell array. Each of the memory layers comprises a first line and a second line, and further includes a memory cell disposed between the first line and the second line and including a variable resistance element. The control unit is configured to, when executing a forming operation on the memory cell array, execute the forming operation sequentially on the plurality of memory layers. The forming operation is executed sequentially on the memory layers in ascending order of a magnitude of a non-selected current flowing in a non-selected memory cell during the forming operation.
    Type: Application
    Filed: March 18, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuhiro NOJIRI, Shigeki Kobayashi, Masaki Yamato, Hiroyuki Fukumizu
  • Publication number: 20140048761
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.
    Type: Application
    Filed: December 28, 2012
    Publication date: February 20, 2014
    Inventors: Yasuhiro NOJIRI, Hiroyuki Fukumizu, Shigeki Kobayashi, Masaki Yamato
  • Publication number: 20140036571
    Abstract: A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.
    Type: Application
    Filed: March 22, 2013
    Publication date: February 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeki KOBAYASHI, Takeshi YAMAGUCHI
  • Patent number: 8617575
    Abstract: Immunity against protozoan is conferred on an animal by a method comprising orally administering to an animal a transformed plant cell comprising a polynucleotide encoding a protective antigen against protozoiasis development, a transformed plant or its progeny or clone comprising the transformed cell, a propagation material of the plant or its progeny or clone, a processed material or extract of the above cell, plant, or its progeny or clone, or propagation material, or a protective antigen against protozoiasis development isolated from the transformed plant cell or the transformed plant or its progeny or clone.
    Type: Grant
    Filed: May 30, 2005
    Date of Patent: December 31, 2013
    Assignees: Kitasato Daiichi Sankyo Vaccine Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Akira Ito, Toru Gotanda, Shigeki Kobayashi, Katsumi Kume, Takeshi Matsumura
  • Publication number: 20130301339
    Abstract: A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second electrode is configured by a P type semiconductor. The control unit, when performing a setting operation of a memory cell, applies a voltage such that a current flows in a direction from the first electrode toward the second electrode.
    Type: Application
    Filed: February 27, 2013
    Publication date: November 14, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki FUKUMIZU, Shigeki Kobayashi, Yasuhiro Nojiri, Masaki Yamato, Takeshi Yamaguchi
  • Patent number: 8575287
    Abstract: To provide a method for producing a PTFE fine powder having a low paste extrusion pressure property by a simple method. The method for producing a PTFE fine power comprises emulsion polymerizing tetrafluoroethylene in the presence of an aqueous medium, a fluorinated surfactant and a radical polymerization initiator, to produce an aqueous PTFE emulsion, and coagulating it in the presence of at least one bulk density-reducing compound selected from the group consisting of ammonia, an ammonium salt and urea in an amount of from 0.4 to 10 parts by mass per 100 parts by mass of PTFE.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: November 5, 2013
    Assignee: Asahi Glass Company, Limited
    Inventors: Shinya Higuchi, Yasuhiko Matsuoka, Shigeki Kobayashi
  • Publication number: 20130182488
    Abstract: A non-volatile semiconductor memory according to an embodiment includes: a data storage unit including a memory cell array and a writing circuit; an encoder that directs the writing circuit to write write data to the memory cell array; a writing determining circuit that determines whether the writing of the write data to the memory cell array within a predetermined number of writing operations fails or succeeds, inverts the write data to generate new write data when the writing of the write data fails, and directs the writing circuit to write the new write data to the memory cell array; a switching circuit that inverts read data which is read from the memory cell to generate new read data when the writing determining circuit determines that the writing of the write data fails; and a decoder that decodes the read data into the information data.
    Type: Application
    Filed: July 9, 2012
    Publication date: July 18, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki KOBAYASHI, Hideyuki Tabata
  • Patent number: 8480453
    Abstract: A die grinder including a body having a longitudinal axis, and a grinding head portion with an output shaft capable of powered rotation. A motor is disposed in the body for rotating the output member. A locking interconnect portion attaches the grinding head portion to the body and is adapted to permit selective rotation of the grinding head portion relative to the body about the longitudinal axis of the body. Thus, the grinding head can be positioned at different selected angles relative to the body.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 9, 2013
    Assignee: SP Air Kabushiki Kaisha
    Inventor: Shigeki Kobayashi
  • Patent number: 8470942
    Abstract: The claimed invention relates to a method for producing a melt-moldable tetrafluoroethylene copolymer containing repeating units (a) based on tetrafluoroethylene and repeating units (b) based on another fluoromonomer, wherein the amount of the repeating units (a), based on the total mass of the repeating units (a) and the repeating units (b), is from 97.3 to 99.5 mass %, and the volume flow rate of the copolymer is from 0.1 to 1000 mm3/s; the process including radical suspension-polymerization of tetrafluoroethylene and the fluoromonomer in an aqueous medium in the presence of a radical polymerization initiator and at least one chain transfer agent selected from the group consisting of methane, ethane, a hydrochlorocarbon, a hydrofluorocarbon and a hydrochlorofluorocarbon.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: June 25, 2013
    Assignee: Asahi Glass Company, Limited
    Inventors: Atsushi Funaki, Shigeki Kobayashi, Hiroki Nagai
  • Patent number: 8379431
    Abstract: A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured by plural memory strings disposed with longer direction extending in a first direction and including plural series-connected memory transistors. Word lines are disposed with a longer direction extending in a second direction orthogonal to the first direction, and connected commonly to the gate electrodes of the plural memory transistors lined up in the second direction. A plate line is disposed to sandwich the variable resistance film with the gate electrode. First voltage terminals supply a certain voltage to first ends of the plural memory strings. Second voltage terminals supply a certain voltage to second ends of the plural memory strings.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Kazuhiko Yamamoto
  • Patent number: 8261849
    Abstract: A power driven tool for rotating a mechanical element. The tool includes a housing and motor. The motor has an output shaft. The shaft rotates relative to the housing. The tool also includes an impact drive axially fixed within the housing. The impact drive includes a base and an anvil shaft having an anvil. The impact drive includes an annular hammer having opposite impact lands pivotally mounted on the base for movement between three positions, including a forward position in which the hammer is positioned so one impact land engages the anvil, a reverse position in which the hammer is positioned so another of the impact lands engages the anvil, and a disengaged position in which neither of the impact lands engages the anvil. Further, the tool includes a ratchet mechanism. The ratchet mechanism includes an output drive mounted for rotation relative to the housing for rotating a mechanical element.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: September 11, 2012
    Assignee: SP Air Kabushiki Kaisha
    Inventor: Shigeki Kobayashi
  • Publication number: 20120223732
    Abstract: There is provided a transmission device. The transmission device includes: an adapter device (11) including: a first surface having a plurality of first terminals (21) thereon; and a second surface opposite to the first surface and having a plurality of second terminals (22) thereon, wherein a pitch between the adjacent second terminals is different from a pitch between the adjacent first terminals, a plurality of signal lines each electrically connecting a corresponding one of the first terminals and a corresponding one of the second terminals; and a signal compensation device (12) connected to the adapter device through the signal lines and configured to compensate for a transmission loss of a signal path between the corresponding first terminal and the corresponding second terminal such that the transmission loss is set to a given value.
    Type: Application
    Filed: February 29, 2012
    Publication date: September 6, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Shigeki Kobayashi
  • Publication number: 20120217461
    Abstract: A semiconductor memory device according to an embodiment includes: first lines provided on a substrate; second lines provided between the first lines and the substrate so as to intersect the first lines; and a first memory cell array including first memory cells, each of the first memory cells being provided at respective intersections of the first lines and the second lines and including a current rectifying element and a variable resistor connected in series. The variable resistor of the first memory cell includes a first recording layer and a second recording layer, the first recording layer being made of an oxide of a first metal material, the second recording layer being made of the first metal material and being formed so as to contact with the first recording layer. The second recording layer is closer to the first line than the first recording layer is.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki KOBAYASHI, Takashi Shigeoka, Mitsuru Sato, Takahiro Hirai, Katsuyuki Sekine, Kazuya Kinoshita, Soichi Yamazaki, Ryota Fujitsuka, Kensuke Takahashi, Yasuhiro Nojiri, Masaki Yamato, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Publication number: 20120217464
    Abstract: A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Kazuhiko Yamamoto, Kenji Aoyama, Shigeto Oshino, Kei Watanabe, Shinichi Nakao, Satoshi Ishikawa, Takeshi Yamaguchi
  • Patent number: 8240394
    Abstract: A power-driven hammer including a body including a tubular housing and a barrel assembly received in the housing. The barrel assembly has an at-rest position relative to the housing. The barrel assembly includes a barrel having a forward end adapted to hold a tool, an opening, and a rearward end. The barrel assembly includes a mass received in the opening of the barrel. The mass moves in the barrel opening when the hammer is operating through a power stroke and a return stroke. The barrel assembly moves forward and rearward from its at-rest position relative to the housing when the hammer is operating. The hammer includes a vibration reducing mechanism connecting the barrel assembly to the body reducing shock transmitted to the housing as the mass moves forward and rearward in the barrel.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: August 14, 2012
    Assignee: SP Air Kabushiki Kaisha
    Inventor: Shigeki Kobayashi
  • Publication number: 20120202906
    Abstract: To produce a PTFE aqueous emulsion, whereby the environmental load is little, the stability of the aqueous emulsion is high, and a molded product having high heat resistance can be obtained. A process for producing a PTFE aqueous emulsion, which comprises emulsion-polymerizing tetrafluoroethylene (TFE) by means of at least one fluorinated emulsifier selected from the group consisting of a C4-8 fluorinated carboxylic acid having from 1 to 4 etheric oxygen atoms in its main chain, and its salts, to obtain an aqueous emulsion containing polytetrafluoroethylene (PTFE) microparticles having an average primary particle size of from 0.1 to 0.3 ?m, wherein at the beginning of the emulsion polymerization of TFE, a (polyfluoroalkyl)ethylene (a) represented by “CH2?CH—Rf1”, and/or a comonomer (b) having a monomer reactivity ratio rTFE of from 0.1 to 8 in copolymerization with tetrafluoroethylene, is incorporated to the emulsion polymerization system, so as to be from 0.001 to 0.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 9, 2012
    Applicant: Asahi Glass Company, Limited
    Inventors: Shinya HIGUCHI, Yasuhiko MATSUOKA, Shigeki KOBAYASHI
  • Patent number: 8118476
    Abstract: A gas/liquid mixing equipment of the present invention comprises a stirring vessel 1, a stirring shaft 10 inserted horizontally in the stirring vessel 1 and a helical ribbon impeller 20 attached to the stirring shaft 10, whereby a high gas absorption performance can be secured even with low shearing. Further, a polymer can be produced with high productivity. A gas/liquid mixing method of the present invention is a method which comprises employing the above-mentioned gas/liquid mixing equipment, and a method for producing a polymer of the present invention is a method which comprises polymerizing feed monomers containing gaseous monomers in aqueous solvents, wherein the gaseous monomers and the aqueous solvents are mixed by such a gas/liquid mixing method. A polymer of the present invention is produced by the above-mentioned method for producing a polymer.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: February 21, 2012
    Assignee: Asahi Glass Company, Limited
    Inventors: Nobuyuki Kasahara, Shin Tatematsu, Shigeki Kobayashi, Yasuhiko Matsuoka, Hiroki Nagai, Terence Edwin Attwood, Steven McDonald, Philip David Mackrell, Shigeki Hiraoka
  • Publication number: 20110235395
    Abstract: A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured by plural memory strings disposed with longer direction extending in a first direction and including plural series-connected memory transistors. Word lines are disposed with a longer direction extending in a second direction orthogonal to the first direction, and connected commonly to the gate electrodes of the plural memory transistors lined up in the second direction. A plate line is disposed to sandwich the variable resistance film with the gate electrode. First voltage terminals supply a certain voltage to first ends of the plural memory strings. Second voltage terminals supply a certain voltage to second ends of the plural memory strings.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 29, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeki KOBAYASHI, Kazuhiko Yamamoto