Patents by Inventor Shigeki Nakamura

Shigeki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10432875
    Abstract: An image processing apparatus includes: a row integration ratio calculation unit that divides a first row integration value by a second row integration value for each row, to calculate a row integration ratio; a reference value generation unit that generates a reference value for each row; a reference value integration unit that multiplies the integration ratio by the reference value for each row and integrates multiplication results corresponding to all rows, to calculate a sum of the multiplication results of the integration ratios and the reference values; a flicker parameter estimation unit that estimates a flicker parameter of flicker generated in the first exposure image on the basis of the sum; and a flicker correction unit that corrects the flicker generated in the first exposure image on the basis of the estimated flicker parameter. The present disclosure can be applied to an image sensor.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 1, 2019
    Assignee: SONY CORPORATION
    Inventors: Shigeki Nakamura, Shun Kaizu
  • Publication number: 20190165482
    Abstract: A radar device includes: a case having an opening at the front in a forward direction, which is a transmission direction of electromagnetic waves; a circuit board placed in the case, the circuit board having first and second circuit board parts, one component side of the first circuit board part facing in the forward direction, the component sides of the second circuit board part extending along the forward direction; a transmission antenna and reception antenna composed of a plurality of antenna elements placed into an array in a direction crossing the forward direction in an area, facing in the forward direction, on the circuit board; and a dielectric lens having a semi-cylindrical or parabolic cylindrical shape in the forward direction, the dielectric lens being placed in the opening in the case so as to extend along a direction in which the plurality of antenna elements are placed into an array.
    Type: Application
    Filed: November 23, 2018
    Publication date: May 30, 2019
    Inventors: RYOSUKE SHIOZAKI, TOMOHIRO YUI, KEN TAKAHASHI, YUICHI KASHINO, KOUJI SUZUKI, NORIAKI SAITO, SHIGEKI NAKAMURA
  • Publication number: 20190165484
    Abstract: A radar device includes: a housing that includes an aperture in a front direction as a transmitting direction of an electromagnetic wave; a circuit board disposed in the housing such that a board surface extends along the front direction; an antenna unit that includes antenna elements being arrayed along a direction intersecting the front direction in a region on a side in the front direction of the circuit board, and that transmits the electromagnetic wave to the outside of the housing through the aperture and receives a reflected wave of the electromagnetic wave; and a dielectric lens that is disposed in the aperture of the housing to extend along a direction in which the antenna elements are arrayed and that has a semi-cylindrical shape or a parabolic-cylindrical shape projecting in the front direction.
    Type: Application
    Filed: November 23, 2018
    Publication date: May 30, 2019
    Inventors: RYOSUKE SHIOZAKI, TOMOHIRO YUI, KEN TAKAHASHI, YUICHI KASHINO, KOUJI SUZUKI, NORIAKI SAITO, SHIGEKI NAKAMURA
  • Publication number: 20190165483
    Abstract: A radar device includes: an antenna unit including antenna elements arrayed along a direction intersecting a front direction in a circuit board, transmitting an electromagnetic wave upward of a board surface of the circuit board, and receiving a reflected wave of the electromagnetic wave; a reflection unit supported above the board surface of the circuit board in a housing, reflecting the electromagnetic wave transmitted from the antenna unit to change a traveling direction of the electromagnetic wave to the front direction, and reflecting the reflected wave from the front direction to change a traveling direction of the reflected wave to a direction toward the antenna unit; and a dielectric lens disposed in an aperture of the housing to extend along a direction in which the antenna elements are arrayed, and having a semi-cylindrical shape or a parabolic-cylindrical shape projecting in the front direction.
    Type: Application
    Filed: November 23, 2018
    Publication date: May 30, 2019
    Inventors: RYOSUKE SHIOZAKI, TOMOHIRO YUI, KEN TAKAHASHI, YUICHI KASHINO, KOUJI SUZUKI, NORIAKI SAITO, SHIGEKI NAKAMURA
  • Publication number: 20190104251
    Abstract: To provide an image sensor capable of guaranteeing consistency between acquired image information and picked-up image information. An image sensor 30 includes an image information processing unit 4 that forms integrated information in which image sensor identification information capable of identifying the image sensor 30 and image information obtained by an analog/digital conversion unit 25 are associated with each other, and an image information output unit 24 that outputs the integrated information to an external unit.
    Type: Application
    Filed: December 27, 2016
    Publication date: April 4, 2019
    Inventors: SEICHI OTSUKI, SHIGEYUKI BABA, SHIGEKI NAKAMURA
  • Publication number: 20180323225
    Abstract: A solid-state imaging device according to the present disclosure includes a pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix form and the unit pixels are grouped into a plurality of pixel groups and a timing controller which independently sets an exposure start timing and an exposure end timing relative to each of the plurality of pixel groups so that at least one pixel group of the plurality of pixel groups is exposed a plurality of times within a single vertical synchronization period.
    Type: Application
    Filed: September 20, 2016
    Publication date: November 8, 2018
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Shigeki Nakamura, Seichi Otsuki
  • Publication number: 20180121076
    Abstract: A drawing processing method of controlling a drawing processing apparatus, the method including: receiving a first touch operation of tapping a first location on a touch panel display; storing, in a memory, the first location as a drawing start location; receiving a second touch operation of sliding on the touch panel display from a second location to a third location to draw a first slide trajectory, the second location being different from the first location; storing, in the memory, the second location as an operation start location; and based on the drawing start location and the operation start location, displaying an object of a second slide trajectory corresponding to the first slide trajectory drawn by the second touch operation such that the displayed object of the second slide trajectory starts from the drawing start location.
    Type: Application
    Filed: October 16, 2017
    Publication date: May 3, 2018
    Applicant: GREE, Inc.
    Inventors: Kazuaki Hamada, Gijun Han, Shigeki Nakamura
  • Patent number: 9917660
    Abstract: A wireless communication device includes a baseband variable gain amplifier that amplifies a transmission baseband signal, a local variable gain amplifier that amplifies a local signal, a frequency-conversion circuit that mixes the amplified transmission baseband signal and the amplified local signal to carry out a frequency conversion into a transmission high-frequency signal, a first detector that detects a power of the transmission high-frequency signal, and a controller that controls at least one of a gain of the transmission baseband variable gain amplifier and a gain of the local variable gain amplifier on the basis of the detected power of the transmission high-frequency signal so that a power of the transmission high-frequency signal to be detected takes a predetermined value.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: March 13, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigeki Nakamura, Noriaki Saito, Taiji Akizuki
  • Publication number: 20170350963
    Abstract: A radar device includes transmission signal generation circuitry that generates one or more transmission signals, a transmission amplifier that amplifies a power level of the one or more transmission signals, a transmission gain controller that adjusts a gain of the transmission amplifier, transmission antenna circuitry that converts each of the one or more amplified transmission signals into each of one or more radio signals and transmit the one or more radio signals to a measurement target space, reception antenna circuitry that receives the one or more radio signals from the measurement target space, and one or more receivers that detect a power level of a transmission/reception leakage signal using the one or more received radio signals. The transmission gain controller adjusts the gain of the transmission amplifier in accordance with a result of comparison between the detected power level and a power level of a transmission/reception leakage signal measured in advance.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 7, 2017
    Inventor: SHIGEKI NAKAMURA
  • Publication number: 20170150030
    Abstract: The present disclosure relates to an image processing apparatus, an image processing method, a program, and an image sensor, which are capable of extracting and correcting a flicker component in one-pass from a frame for flicker correction, while reducing a necessary memory capacity as much as possible.
    Type: Application
    Filed: July 17, 2015
    Publication date: May 25, 2017
    Inventors: SHIGEKI NAKAMURA, SHUN KAIZU
  • Patent number: 9659346
    Abstract: An image processing apparatus includes: a target position selecting unit to select a pixel position on an input image, as a target position; a candidate line setting unit to set two or more sets of candidate lines including a pixel with a value, in the vicinity of the target position; a weighted-value calculating unit to calculate a weighted value that corresponds to a degree of expectation that the target position and the pixel position on the candidate line are on the same pattern; a direction classifying unit to selectively determine a set of candidate lines that are close to a direction of a pattern of the target position in accordance with the weighted value of each pixel on the candidate lines; and a first interpolated-value calculating unit to calculate a pixel value of the target position in accordance with the weighted value of each pixel on the candidate lines.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: May 23, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shigeki Nakamura, Yasunobu Hitomi, Tomoo Mitsunaga
  • Patent number: 9654063
    Abstract: A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 16, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukio Okazaki, Masakatsu Maeda, Shigeki Nakamura, Akinori Daimo
  • Patent number: 9525581
    Abstract: In signal processing of the present disclosure, an abnormal correction value as a correction value for correcting a quadrature error that occurs in quadrature modulation is output in malfunction determining processing, and a normal correction value as the correction value is output in calibration processing. The presence or absence of malfunction in the signal processing is determined on the basis of the levels of carrier leak and image leak of the quadrature modulated signal.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: December 20, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Noriaki Saito, Kenji Miyanaga, Shigeki Nakamura
  • Publication number: 20160344484
    Abstract: A wireless communication device includes a baseband variable gain amplifier that amplifies a transmission baseband signal, a local variable gain amplifier that amplifies a local signal, a frequency-conversion circuit that mixes the amplified transmission baseband signal and the amplified local signal to carry out a frequency conversion into a transmission high-frequency signal, a first detector that detects a power of the transmission high-frequency signal, and a controller that controls at least one of a gain of the transmission baseband variable gain amplifier and a gain of the local variable gain amplifier on the basis of the detected power of the transmission high-frequency signal so that a power of the transmission high-frequency signal to be detected takes a predetermined value.
    Type: Application
    Filed: May 10, 2016
    Publication date: November 24, 2016
    Inventors: SHIGEKI NAKAMURA, NORIAKI SAITO, TAIJI AKIZUKI
  • Publication number: 20160285669
    Abstract: In signal processing of the present disclosure, an abnormal correction value as a correction value for correcting a quadrature error that occurs in quadrature modulation is output in malfunction determining processing, and a normal correction value as the correction value is output in calibration processing. The presence or absence of malfunction in the signal processing is determined on the basis of the levels of carrier leak and image leak of the quadrature modulated signal.
    Type: Application
    Filed: February 8, 2016
    Publication date: September 29, 2016
    Inventors: NORIAKI SAITO, KENJI MIYANAGA, SHIGEKI NAKAMURA
  • Patent number: 9369088
    Abstract: An amplifier is disclosed that avoids an increase in circuit scale and an increase in power consumption, and easily avoids the odd-order harmonics. This amplifier includes a MOS transistor including a plurality of gate fingers or a plurality of MOS transistors each including a single gate finger; a dielectric capacitor that is added to each of the gate fingers; and a variable resistor that is connected between an input terminal to which an AC signal is input, and a gate input terminal. In the amplifier, the variable resistor, gate resistors of the respective gate fingers, and the dielectric capacitors form a plurality of low pass filters having desired frequency characteristics, and the gate fingers are different from each other in width or length from the gate input terminal to an oxide diffusion (OD) area boundary.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: June 14, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Kouji Takahashi, Shigeki Nakamura
  • Publication number: 20160142014
    Abstract: A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.
    Type: Application
    Filed: October 16, 2015
    Publication date: May 19, 2016
    Inventors: YUKIO OKAZAKI, MASAKATSU MAEDA, SHIGEKI NAKAMURA, AKINORI DAIMO
  • Patent number: 9236858
    Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 12, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeki Nakamura, Shintaro Mori, Yoshinori Tokioka, Kenji Tokami
  • Publication number: 20150371961
    Abstract: A semiconductor device capable of, regardless of frequency, suppressing propagation of unnecessary signals to a semiconductor element or a semiconductor circuit through a semiconductor substrate, and of suppressing deterioration of signal quality of the semiconductor device caused by parasitic capacitive coupling. The semiconductor device is provided with a semiconductor substrate (100), a semiconductor element (105) which is provided on the surface portion of the semiconductor substrate (100) and which emits signals, a signal line (103) which is connected to the semiconductor element (105), and a polysilicon layer (102) which is provided between the semiconductor substrate (100) and the signal line (103).
    Type: Application
    Filed: November 29, 2013
    Publication date: December 24, 2015
    Inventors: Shigeki NAKAMURA, Kouji TAKAHASHI
  • Patent number: D766132
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: September 13, 2016
    Assignees: Toyota Jidosha Kabushiki Kaisha, Mazda Motor Corporation
    Inventors: Kosuke Kubo, Shinichi Isayama, Atsushi Shudo, Shigeki Nakamura, Tadashi Ozeki, Eijirou Mitsuyasu