Abstract: An apparatus capable of improving the estimation accuracy of information on a subject including a distance up to the subject is provided. According to an environment recognition apparatus 1 of the present invention, a first cost function is defined as a decreasing function of an object point distance Z. Thus, the longer the object point distance Z is, the lower the first cost of a pixel concerned is evaluated. This reduces the contribution of the first cost of a pixel highly probable to have a large measurement or estimation error of the object point distance Z to the total cost C. Thereby, the estimation accuracy of a plane parameter ^q representing the surface position and posture of the subject is improved.

Abstract: A motion calculation device includes an image-capturing unit configured to capture an image of a range including a plane and outputs the captured image, an extraction unit configured to extract a region of the plane from the image, a detection unit configured to detect feature points and motion vectors of the feature points from a plurality of images captured by the image-capturing unit at a predetermined time interval; and a calculation unit configured to calculate the motion of the host device based on both of an epipolar constraint relating to the feature points and a homography relating to the region.

Abstract: The present invention provides a three-dimensional surface generation method that directly and efficiently generates a three-dimensional surface of the object surface from multiple images capturing a target object. The three-dimensional surface generation method of the present invention sets one image as a basis image from multiple images obtained by capturing the target object from different viewpoint positions and sets other images as reference images, and then generates two-dimensional triangle meshes on the basis image.

Abstract: An apparatus for forming silicon oxide film is disclosed. The apparatus includes a spin coating unit, a carrying unit, and an oxidation unit. The spin coating unit forms a polymer film above a substrate by spin coating a solution including a polymer containing a silazane bond dissolved in an organic solvent. The carrying unit carries the substrate to the oxidation unit without contacting the polymer film. The oxidation unit, when receiving the substrate from the carrying unit, converts the polymer film into the silicon oxide film by either immersing the polymer film with a heated aqueous solution containing hydrogen peroxide, spraying the heated aqueous solution containing hydrogen peroxide over the polymer film, or exposing the polymer film to a reaction gas containing a hydrogen peroxide vapor. The apparatus, by itself, completes the polymer film formation and the polymer-to-silicon oxide film conversion within the apparatus itself.

Abstract: A method for performing a convergence calculation using a projective transformation between images captured by two cameras to observe a flat part of an object in the images, wherein a computational load is reduced while securing a convergence property of the convergence calculation. Initial values (n0(i), d0(i)) are set to values satisfying a limiting condition that should be satisfied by the initial values (n0(i), d0(i)), where the limiting condition is that a plane ?a(i) defined by the initial values (n0(i), d0(i)) of given types of parameters (n(i), d(i)) of a projective transformation matrix in the convergence calculation is inclined with respect to an actual plane including the flat part of the object to be observed.

Abstract: A robot capable of performing appropriate movement control while reducing arithmetic processing for recognizing the shape of a floor. The robot sets a predetermined landing position of steps of the legs on a present assumed floor, which is a floor represented by floor shape information used for a current motion control of the robot, during movement of the robot. An image projection area is set, and is projected on each image captured by cameras mounted on the robot for each predetermined landing position in the vicinity of each of the predetermined landing positions. Shape parameters representing the shape of an actual floor partial area are estimated, forming an actual floor whose image is captured in each partial image area, based on the image of the partial image area generated by projecting the set image projection area on the images captured by the cameras for each partial image area.

Abstract: A motion calculation device includes an image-capturing unit configured to capture an image of a range including a plane and outputs the captured image, an extraction unit configured to extract a region of the plane from the image, a detection unit configured to detect feature points and motion vectors of the feature points from a plurality of images captured by the image-capturing unit at a predetermined time interval; and a calculation unit configured to calculate the motion of the host device based on both of an epipolar constraint relating to the feature points and a homography relating to the region.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: The present invention provides a three-dimensional surface generation method that directly and efficiently generates a three-dimensional surface of the object surface from multiple images capturing a target object. The three-dimensional surface generation method of the present invention sets one image as a basis image from multiple images obtained by capturing the target object from different viewpoint positions and sets other images as reference images, and then generates two-dimensional triangle meshes on the basis image.

Abstract: A robot capable of performing appropriate movement control while reducing arithmetic processing for recognizing the shape of a floor. The robot sets a predetermined landing position of steps of the legs on a present assumed floor, which is a floor represented by floor shape information used for a current motion control of the robot, during movement of the robot. An image projection areas is set, and is projected on each image captured by cameras mounted on the robot for each predetermined landing position in the vicinity of each of the predetermined landing positions. Shape parameters representing the shape of an actual floor partial area are estimated, forming an actual floor whose image is captured in each partial image area, of based on the image of the partial image area generated by projecting the set image projection area on the images captured by the cameras for each partial image area.

Abstract: A method for performing a convergence calculation using a projective transformation between images captured by two cameras to observe a flat part of an object in the images, wherein a computational load is reduced while securing a convergence property of the convergence calculation. Initial values (n0(i), d0(i)) are set to values satisfying a limiting condition that should be satisfied by the initial values (n0(i), d0(i)), where the limiting condition is that a plane ?a(i) defined by the initial values (n0(i), d0(i)) of given types of parameters (n(i), d(i)) of a projective transformation matrix in the convergence calculation is inclined with respect to an actual plane including the flat part of the object to be observed.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: There are provided a plurality of first connection lines arranged in parallel with each other in a same layer, each connecting to a different contact portion; a plurality of second connection lines arranged in parallel with each other in the same layer as the first connection lines, the first connection lines and the second connection lines being arranged in an alternating fashion, and each of the second connection lines connecting to a different contact portion; a plurality of first metal wiring lines connecting to the first connection lines via first plugs; and a plurality of second metal wiring lines formed in a layer different from that of the first metal wiring lines, and connecting to the second connection lines via second plugs, the first metal wiring lines and the second metal wiring lines differing from each other with respect to at least one of thickness and width, or with respect to resistivity of wiring materials, and a product of a wiring capacitance between adjacent two of the first metal wiring

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: A semiconductor design/fabrication system which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising: a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known; a chip information calculator which calculates a sum of the critical areas on each of the selected function blocks; an yield calculator which calculates an yield based on a calculation result of the chip information calculator and defect occurrence rate information of a chip fabrication line; a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of the yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and a combination selector which