Abstract: There are provided a plurality of first connection lines arranged in parallel with each other in a same layer, each connecting to a different contact portion; a plurality of second connection lines arranged in parallel with each other in the same layer as the first connection lines, the first connection lines and the second connection lines being arranged in an alternating fashion, and each of the second connection lines connecting to a different contact portion; a plurality of first metal wiring lines connecting to the first connection lines via first plugs; and a plurality of second metal wiring lines formed in a layer different from that of the first metal wiring lines, and connecting to the second connection lines via second plugs, the first metal wiring lines and the second metal wiring lines differing from each other with respect to at least one of thickness and width, or with respect to resistivity of wiring materials, and a product of a wiring capacitance between adjacent two of the first metal wiring

Abstract: A semiconductor design/fabrication system which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising: a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known; a chip information calculator which calculates a sum of the critical areas on each of the selected function blocks; an yield calculator which calculates an yield based on a calculation result of the chip information calculator and defect occurrence rate information of a chip fabrication line; a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of the yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and a combination selector which

Abstract: Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer.

Abstract: A semiconductor integrated circuit device includes a p-silicon substrate, an n-buried layer formed in the substrate to divide the substrate into an upper region and a lower region, a trench formed from the surface of the substrate to the lower region of the substrate through the buried layer, and an electrode formed in the trench. The electrode forms an n-inversion layer using the buried layer as a carrier source, in the lower region of the semiconductor substrate by a field effect. The n-inversion layer constitutes a capacitor together with the electrode.

Abstract: A silicon film is deposited using low pressure chemical vapor deposition (LPCVD) to fill in openings formed in a substrate such as an insulating film. An aluminum film and a metal film are then formed on the silicon film. A thermal process is then carried out. This thermal process causes the deposited aluminum to replace the silicon in the openings because the silicon migrates to the metal and forms a metal silicide film. The aluminum which replaces the silicon in the openings has few or no voids. The metal silicide film any remaining portion of the aluminum film are then removed using CMP, for example.

Abstract: A manufacturing method of semiconductor devices according to this invention, comprises the step of forming pattern portions containing internal wiring layers on a semiconductor substrate, the step of forming interlayer insulating films on said semiconductor substrate, the step of forming an opening portion in said interlayer insulating films so as to allow the pattern portions and the substrate to appear, and the step of forming a sidewall insulating film on the sidewall of the pattern portions appearing in the opening portion.