Patents by Inventor Shigeo Ohshima
Shigeo Ohshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8179730Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.Type: GrantFiled: December 8, 2010Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuui Shimizu, Shigeo Ohshima, Mie Matsuo
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Patent number: 8000155Abstract: The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.Type: GrantFiled: January 13, 2011Date of Patent: August 16, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshiaki Edahiro, Kazushige Kanda, Naoya Tokiwa, Takuya Futatsuyama, Koji Hosono, Shigeo Ohshima
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Patent number: 7986557Abstract: A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.Type: GrantFiled: July 31, 2009Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Naoya Tokiwa, Shigeo Ohshima
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Publication number: 20110103135Abstract: The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.Type: ApplicationFiled: January 13, 2011Publication date: May 5, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Toshiaki EDAHIRO, Kazushige Kanda, Naoya Tokiwa, Takuya Futatsuyama, Koji Hosono, Shigeo Ohshima
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Publication number: 20110074494Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.Type: ApplicationFiled: December 8, 2010Publication date: March 31, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuui Shimizu, Shigeo Ohshima, Mie Matsuo
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Patent number: 7911823Abstract: A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.Type: GrantFiled: May 20, 2008Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Futatsuyama, Koji Hosono, Toshiaki Edahiro, Naoya Tokiwa, Kazushige Kanda, Shigeo Ohshima
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Patent number: 7889537Abstract: The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.Type: GrantFiled: May 9, 2008Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshiaki Edahiro, Kazushige Kanda, Naoya Tokiwa, Takuya Futatsuyama, Koji Hosono, Shigeo Ohshima
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Patent number: 7869240Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.Type: GrantFiled: June 19, 2008Date of Patent: January 11, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuui Shimizu, Shigeo Ohshima, Mie Matsuo
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Patent number: 7823105Abstract: A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.Type: GrantFiled: November 27, 2007Date of Patent: October 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Ohshima, Kiminobu Suzuki, Kazuhiro Yamada, Takamichi Arizono
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Patent number: 7817457Abstract: According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.Type: GrantFiled: June 4, 2008Date of Patent: October 19, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Naoya Tokiwa, Kazushige Kanda, Toshiaki Edahiro, Koji Hosono, Takuya Futatsuyama, Shigeo Ohshima
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Patent number: 7800967Abstract: This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers.Type: GrantFiled: November 28, 2008Date of Patent: September 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Satoru Takase, Shigeo Ohshima
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Patent number: 7739634Abstract: The verification equipment of a semiconductor integrated circuit in the present invention is included with a circuit net list extraction section that extracts the net list of a circuit, a circuit simulation execution section that executes a circuit simulation, based on the extracted net list, a finite impedance judgment section that judges existence or nonexistence of finite impedances, a floating error terminal judgment section that judges existence or nonexistence of floating error terminals by measuring finite impedances, a true floating error terminal judgment section that adds any one of a P channel-type transistor and an N channel-type transistor to terminals of the circuit where it is judged that there are floating error terminals and calculates changes in potential at the terminals and adds the other of the P channel-type transistor and the N channel-type transistor to the terminals and calculates changes in potential at the terminals, and an output section that outputs a judgment result of the floatiType: GrantFiled: April 30, 2007Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Ohshima, Kiminobu Suzuki
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Patent number: 7732930Abstract: A semiconductor device including a circuit substrate including n number of terminals; a semiconductor chip provided on the circuit substrate and including n number of terminals; and a relay chip including a triangular substrate having a first side, a second side and a third side which form triangle, n number of first terminals located along the first side, n number of second terminals located along the second side, and a plurality of wires connecting the first terminals and the second terminals respectively; a first wire connecting each of the n number of terminals of the circuit substrate to a corresponding first terminal among the n number of first terminals; and a second wire connecting each of the n number of terminals of the semiconductor chip to a corresponding second terminal among the n number of second terminals.Type: GrantFiled: September 6, 2007Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Eiichi Makino, Shigeo Ohshima, Naohisa Okumura
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Publication number: 20100027341Abstract: A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.Type: ApplicationFiled: July 31, 2009Publication date: February 4, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoya TOKIWA, Shigeo OHSHIMA
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Patent number: 7602651Abstract: This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.Type: GrantFiled: December 10, 2007Date of Patent: October 13, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Eiichi Makino, Shigeo Ohshima
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Publication number: 20090175077Abstract: This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers.Type: ApplicationFiled: November 28, 2008Publication date: July 9, 2009Applicant: KABUSHIKI KAISHA THOSHIBAInventors: Satoru TAKASE, Shigeo OHSHIMA
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Publication number: 20090052227Abstract: The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.Type: ApplicationFiled: May 9, 2008Publication date: February 26, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Toshiaki Edahiro, Kazushige Kanda, Naoya Tokiwa, Takuya Futatsuyama, Koji Hosono, Shigeo Ohshima
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Publication number: 20090003103Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.Type: ApplicationFiled: June 19, 2008Publication date: January 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuui SHIMIZU, Shigeo Ohshima, Mie Matsuo
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Publication number: 20080291716Abstract: A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.Type: ApplicationFiled: May 20, 2008Publication date: November 27, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takuya Futatsuyama, Koji Hosono, Toshiaki Edahiro, Naoya Tokiwa, Kazushige Kanda, Shigeo Ohshima
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Publication number: 20080151640Abstract: This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.Type: ApplicationFiled: December 10, 2007Publication date: June 26, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Eiichi MAKINO, Shigeo Ohshima