Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: The present application discloses an inertial sensor comprising a proof mass, an anchor, a flexible member and several sensing electrodes. The anchor is positioned on one side of the sensing, mass block in a first axis. The flexible member is connected to the anchor point and extends along the first axis towards the proof mass to connect the proof mass, in which the several sensing electrodes are provided. In this way, the present application can effectively solve the problems of high difficulty in the production and assembly of inertial sensors and poor product reliability thereof.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Abstract: A brushless motor assembly includes a motor body, a circuit board, and a plurality of electronic elements. The circuit board is disposed on the motor body and has a first surface and a second surface which face opposite directions. The first surface faces the motor body. The second surface has a plurality of thermoconductive layouts. The electronic elements include a plurality of power switching elements disposed on the second surface. A plurality of heat sinks is disposed on the second surface. Each of the power switching elements and each of the heat sinks are connected to each of the thermoconductive layouts, so that a thermal energy generated by each of the power switching elements is transferred to each of the heat sinks through each of the thermoconductive layouts. This configuration thereby reduces an overall volume of the brushless motor assembly.

Abstract: An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.

Abstract: A power tool includes a first connecting port, a second connecting port, a motor module, a first switching member, a second switching member, and a control device. The first switching member is connected between the motor module and the first connecting port. The second switching member is connected between the motor module and the second connecting port. The control device is connected to the first switching member and the second switching member. A control method thereof includes: switch on the first switching member and the second switching member when the control device determines that both the first connecting port and the second connecting port are respectively connected to a battery and a difference between voltages inputted to the first connecting port and the second connecting port is smaller than a predetermined voltage difference, allowing two batteries to supply power to the motor module at the same time.

Abstract: A method includes forming a first transistor of a first semiconductor device. The first semiconductor device includes a first channel region and a gate electrode on the first channel region. A second semiconductor device is bonded to the first semiconductor device by a bonding layer disposed between the first and second semiconductor devices. A second transistor of the second semiconductor device is formed that includes a second channel region and a second gate electrode on the second channel region. The bonding layer is disposed between the first gate electrode of the first transistor and the second gate electrode of the second transistor.

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem.

Abstract: A PPR memory location reporting system includes BIOS coupled to a non-volatile memory system and a volatile memory system. During boot operations, the BIOS identifies a memory location identifier in the non-volatile memory system for a memory location that is included in the volatile memory system and that is associated with PPR, performs PPR operations on the memory location, and determines that the PPR operations on the memory location have failed. In response to determining that the PPR operations on the memory location have failed, the BIOS stores the memory location identifier in a boot error report table that is configured for use by an operating system to prevent use of the memory location by the operating system, and reserves the memory location identifier in a memory map that is configured for use by the operating system to prevent use of the memory location by the operating system.

Abstract: A transistor includes a gate structure, a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, source/drain contacts laterally spaced apart from the gate structure and disposed laterally next to the channel layer, and a spacer laterally interposed between the gate structure and the source/drain contacts. A semiconductor device and a semiconductor structure are also provided.

Abstract: A power tool includes a case, a motor, a plurality of Hall effect sensors, a first circuit board, and a second circuit board. The Hall effect sensors detect a position of a rotor of the motor and correspondingly generate position signals. A plurality of commutating switches and a first controller are disposed on the first circuit board. A second controller is disposed on the second circuit board, and could transmit a driving signal to the first controller according to the operating signal of an operator interface. The first controller regulates the commutating switches to commutate according to the driving signal and the position signals, thereby to activate the rotor to rotate. With such design, a commutation process and a user operating process are regulated by the two different controllers, which could efficiently simplify the program code installed in each of the controllers and facilitate the maintenance of the controllers.

Abstract: An information handling system includes a plurality of persistent memory devices and a basic input/output system (BIOS). The BIOS begins a power-on self-test (POST) of the information handling system. During the POST, the BIOS may call a block input/output (I/O) driver to access a memory region within the first persistent memory device. The access of the memory region within the first persistent memory device is to determine whether the first persistent memory device is a bootable persistent memory device. The BIOS may determine whether blocks of the memory region contain bad memory locations. In response to the memory region containing bad memory locations, the BIOS may return a device error message without performing the access of the blocks of the memory region within the first persistent memory device and may boot to an operating system of the information handling system via another bootable device.

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem.

Abstract: An information handling system includes a processor, a plurality of dual in-line memory modules (DIMMs), and a basic input/output system (BIOS). During a power-on self-test (POST), the BIOS may read serial presence detect data from each of the DIMMs, determine a total amount of installed memory. The BIOS may determine whether the total amount of the installed memory exceeds a maximum memory capacity of the processor. If so, the BIOS may remove memory capacity of the DIMMs to create a second total amount of the installed memory that is less than the maximum memory capacity of the processor, configure a memory address decode register with the second total amount of the installed memory, and complete the POST.

Abstract: A memory scrubbing system includes a persistent memory device coupled to an operating system (OS) and a Basic Input/Output System (BIOS). During a boot process and prior to loading the OS, the BIOS retrieves a known memory location list that identifies known memory locations of uncorrectable errors in the persistent memory device and performs a partial memory scrubbing operation on the known memory locations. The BIOS adds any known memory locations that maintain an uncorrectable error to a memory scrub error list. The BIOS then initiates a full memory scrubbing operation on the persistent memory device, cause the OS to load and enter a runtime environment while the full memory scrubbing operation is being performed, and provides the memory scrub error list to the OS.

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem.

Abstract: An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.