Abstract: A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

Abstract: A method for manufacturing a composite fabric includes the steps of feeding, mixing and stirring, first drying, hot melt extrusion, first cooling, stretch extension, second cooling, winding-strands-into-roll, second drying, and weaving. The composite fabric is composed of multiple first threads and multiple second threads which are woven to the first threads. The first threads and the second threads are respectively reflective threads and glowing threads so that the composite fabric includes both features of light reflection and glowing in dark.

Abstract: A wire drawing process of a light storage wire includes a feeding step, a mixing step, a first drying step, a hot melt extrusion step, a first cooling step, a shaping/organizing wire step, a hot-temperature remodeling step, a stretching step, a second cooling step, a strand winding/rolling step, and a second drying step.

Abstract: An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.

Abstract: The thread drawing processes include the steps of feeding, mixing and stirring, first drying, hot melt extrusion, first cooling, stretch extension, second cooling, winding-strands-into-roll, and second drying. The threads made by the processes mainly use thermoplastic polyurethane particles which are easily prepared. When fabric made by the threads is attached to objects, the fabric is flat and neat.

Abstract: The adhesive thread drawing processes include the steps of feeding, mixing and stirring, first drying, hot melt extrusion, first cooling, stretch extension, second cooling, winding-strands-into-roll, and second drying. The threads made by the processes are woven into fabric which has a certain level of stickiness so as to be attached onto objects without using glue and adhesive, and the fabric is flat and neat when it is attached to an object.

Abstract: An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.

Abstract: A PPR memory location reporting system includes BIOS coupled to a non-volatile memory system and a volatile memory system. During boot operations, the BIOS identifies a memory location identifier in the non-volatile memory system for a memory location that is included in the volatile memory system and that is associated with PPR, performs PPR operations on the memory location, and determines that the PPR operations on the memory location have failed. In response to determining that the PPR operations on the memory location have failed, the BIOS stores the memory location identifier in a boot error report table that is configured for use by an operating system to prevent use of the memory location by the operating system, and reserves the memory location identifier in a memory map that is configured for use by the operating system to prevent use of the memory location by the operating system.

Abstract: A detection method for electronic devices including steps as follows is provided. The detection method includes: providing an electronic device substrate; attaching a portion of electronic devices of the electronic device substrate through an electronic device transfer module, wherein the electronic device transfer module includes a plurality of detecting elements corresponding to the portion of the electronic devices, and each of the detecting elements includes at least one pair of electrodes; detecting whether a conducting path between the at least one pair of electrodes is generated or not to confirm a status of contact between the portion of the electronic devices and a contact target; and transferring the portion of the electronic devices attached to the electronic device transfer module to a target substrate. An electronic device transfer module having detecting elements is also provided.

Abstract: A brushless motor assembly includes a motor body, a circuit board, and a plurality of electronic elements. The circuit board is disposed on the motor body and has a first surface and a second surface which face opposite directions. The first surface faces the motor body. The second surface has a plurality of thermoconductive layouts. The electronic elements include a plurality of power switching elements disposed on the second surface. A plurality of heat sinks is disposed on the second surface. Each of the power switching elements and each of the heat sinks are connected to each of the thermoconductive layouts, so that a thermal energy generated by each of the power switching elements is transferred to each of the heat sinks through each of the thermoconductive layouts. This configuration thereby reduces an overall volume of the brushless motor assembly.

Abstract: A PPR memory location reporting system includes BIOS coupled to a non-volatile memory system and a volatile memory system. During boot operations, the BIOS identifies a memory location identifier in the non-volatile memory system for a memory location that is included in the volatile memory system and that is associated with PPR, performs PPR operations on the memory location, and determines that the PPR operations on the memory location have failed. In response to determining that the PPR operations on the memory location have failed, the BIOS stores the memory location identifier in a boot error report table that is configured for use by an operating system to prevent use of the memory location by the operating system, and reserves the memory location identifier in a memory map that is configured for use by the operating system to prevent use of the memory location by the operating system.

Abstract: A wire drawing process of a light storage wire includes a feeding step, a mixing step, a first drying step, a hot melt extrusion step, a first cooling step, a shaping/organizing wire step, a hot-temperature remodeling step, a stretching step, a second cooling step, a strand winding/rolling step, and a second drying step.

Abstract: An unavailable memory device initialization system includes a memory controller device that is configured to determine whether a memory system includes unavailable memory devices during initialization operations. During the first initialization operations, a BIOS engine identifies unavailable memory device(s) in the memory system that were determined to be unavailable by the memory controller device during the first initialization operations and, in response, stores respective unavailable memory device identifier(s) associated with each unavailable memory device in a non-volatile storage subsystem.

Abstract: A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

Abstract: An information handling system includes a non-volatile dual in-line memory module (NVDIMM) and a processor. The NVDIMM instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated on the information handling system. The second partition is accessible to the operating system. The first partition includes a first region and a second region. The processor boots the information handling system to configure the NVDIMM based upon information from the first region, detects an error associated with the NVDIMM, and writes information associated with the error to the second region.

Abstract: A memory scrubbing system includes a persistent memory device coupled to an operating system (OS) and a Basic Input/Output System (BIOS). During a boot process and prior to loading the OS, the BIOS retrieves a known memory location list that identifies known memory locations of uncorrectable errors in the persistent memory device and performs a partial memory scrubbing operation on the known memory locations. The BIOS adds any known memory locations that maintain an uncorrectable error to a memory scrub error list. The BIOS then initiates a full memory scrubbing operation on the persistent memory device, cause the OS to load and enter a runtime environment while the full memory scrubbing operation is being performed, and provides the memory scrub error list to the OS.

Abstract: The thread drawing processes include the steps of feeding, mixing and stirring, first drying, hot melt extrusion, first cooling, stretch extension, second cooling, winding-strands-into-roll, and second drying. The threads made by the processes mainly use thermoplastic polyurethane particles which are easily prepared. When fabric made by the threads is attached to objects, the fabric is flat and neat.

Abstract: A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.

Abstract: A memory scrubbing system includes a persistent memory device coupled to an operating system (OS) and a Basic Input/Output System (BIOS). During a boot process and prior to loading the OS, the BIOS retrieves a known memory location list that identifies known memory locations of uncorrectable errors in the persistent memory device and performs a partial memory scrubbing operation on the known memory locations. The BIOS adds any known memory locations that maintain an uncorrectable error to a memory scrub error list. The BIOS then initiates a full memory scrubbing operation on the persistent memory device, cause the OS to load and enter a runtime environment while the full memory scrubbing operation is being performed, and provides the memory scrub error list to the OS.

Abstract: A facial expression modeling method used in a facial expression modeling apparatus is provided that includes the steps outlined below. Two two-dimensional images of a facial expression retrieved by two image retrieving modules respectively are received. A deep learning process is performed on the two two-dimensional images to generate a disparity map. The two two-dimensional images and the disparity map are concatenated to generate a three-channel feature map. The three-channel feature map is processed by a weighting calculation neural network to generate a plurality of blend-shape weightings. A three-dimensional facial expression is modeled according to the blend-shape weightings.