Abstract: A resistor circuit, an artificial intelligence chip and a method for manufacturing the same are provided. The resistor circuit includes a stack structure. The stack structure includes resistive material layers and insulating layers stacked alternately. The resistor circuit includes at least two unit resistors electrically connected in series or parallel. The at least two unit resistors are respectively defined in the resistive material layers of different layers.

Abstract: A technology for cleaning a training data set for a neural network using dirty training data starts by accessing a labeled training data set that includes relatively dirty labeled data elements. The labeled training data set is divided into a first subset A and a second subset B. The procedure includes cycling between the subsets A and B, including producing refined model-filtered subsets of subsets A and B to provide a cleaned data set. Each refined model-filtered subset can have improved cleanliness and increased numbers of elements.

Abstract: A three-way switch array structure including N first connectors, M second connectors, N×M third connectors and N×M three-way switches is provided, each three-way switch has a first terminal, a second terminal, a third terminal, a first switch and a second switch. Each of first terminals is disposed on one of the first connectors, each of second terminals is disposed on one of the second connectors, and each of third terminals is disposed on one of the third connectors, the first switch is disposed between the first terminal and the third terminal, and the second switch is disposed between the second terminal and the third terminal, wherein N and M are positive integers greater than or equal to 1.

Abstract: A semiconductor device and a method for forming such are provided, the device including: a substrate, a plurality of parallel active semiconductor patterns that extend through a drain-side region and a source-side region, a metal drain contact in the drain-side region, an active gate pattern, a first dummy gate pattern, and a second dummy gate pattern that all extend across the active semiconductor patterns, and a metal interconnect structure located in a region between the first and the second dummy gate patterns. The active semiconductor patterns are doped with a dopant in portions exposed by the dummy gates in dummy gate regions that include the gate cut regions of the first and second dummy gate patterns. The metal interconnect structure connects each of a second subset of the active semiconductor patterns to a respective at least one of a first subset of the active semiconductor patterns.

Abstract: A memory device includes a periphery wafer, a memory array chip stack, and a plurality of first conductive contacts. The periphery wafer has a functional surface. The memory array chip stack is disposed on the periphery wafer and has a functional surface, in which the functional surface of the periphery wafer faces toward the functional surface of the memory array chip stack, and a first side of the memory array chip stack is in a staircase configuration. The first conductive contacts are on the first side of the memory array chip stack, and between and interconnecting the functional surface of the periphery wafer and the functional surface of the memory array chip stack.

Abstract: A memory device and a manufacturing method for the same are provided. The memory device includes a stacked body structure and a staircase structure. The stacked body structure includes a first sub-stacked body structure and a second sub-stacked body structure. The staircase structure is electrically connected to the stacked body structure. The staircase structure includes a first sub-staircase structure and a second sub-staircase structure. Each of the first sub-staircase structure and the second sub-staircase structure includes a first staircase portion and a second staircase portion. The first sub-stacked body structure and the second sub-stacked body structure are respectively connected to the first staircase portion of the first sub-staircase structure and the first staircase portion of the second sub-staircase structure.

Abstract: A memory device includes a periphery wafer, a memory array chip stack, and a plurality of first conductive contacts. The periphery wafer has a functional surface. The memory array chip stack is disposed on the periphery wafer and has a functional surface, in which the functional surface of the periphery wafer faces toward the functional surface of the memory array chip stack, and a first side of the memory array chip stack is in a staircase configuration. The first conductive contacts are on the first side of the memory array chip stack, and between and interconnecting the functional surface of the periphery wafer and the functional surface of the memory array chip stack.

Abstract: A neuromorphic computing device includes synapse weights. The synapse weights have different weight values resulted from different transistor arrangements of the synapse weights.

Abstract: A technology for cleaning a training data set for a neural network using dirty training data starts by accessing a labeled training data set that comprises relatively dirty labeled data elements. The labeled training data set is divided into a first subset A and a second subset B. The procedure includes cycling between the subsets A and B, including producing refined model-filtered subsets of subsets A and B to provide a cleaned data set. Each refined model-filtered subset can have improved cleanliness and increased numbers of elements.

Abstract: A method for generating a classification model using a training data set. An iterative procedure for training an ANN model, in which an iteration includes selecting a small sample of training data from a source of training data, training the model using the sample, using the model in inference mode over a larger sample of the training data, and reviewing the results of the inferencing. The results can be evaluated to determine whether the model is satisfactory, and if it does not meet specified criteria, then cycles of sampling, training, inferencing and reviewing results (STIR cycles) are repeated in an iterative process until the criteria are met. A classification engine trained as described herein is provided.

Abstract: A multilayer structure includes a substrate and a plurality of sub-stacks extending along a first direction respectively and disposed on an upper surface of the substrate along a second direction. Each of the sub-stacks includes insulating layers and patterned sacrificial layers alternately stacked on the upper surface along a third direction; conductive layers alternately stacked on the upper surface with the insulating layers along the third direction; and interlayer connectors extending along the third direction; wherein the patterned sacrificial layers have first sides and second sides opposite to the first sides, the conductive layers include first side conductive layers corresponding to the first sides and second side conductive layers corresponding to the second sides; wherein the interlayer connectors are electrically connected and directly contact corresponding ones of the conductive layers, and the first direction, the second direction, and the third direction are crossed.

Abstract: A multilayer structure includes a substrate and a plurality of sub-stacks extending along a first direction respectively and disposed on an upper surface of the substrate along a second direction. Each of the sub-stacks includes insulating layers and patterned sacrificial layers alternately stacked on the upper surface along a third direction; conductive layers alternately stacked on the upper surface with the insulating layers along the third direction; and interlayer connectors extending along the third direction; wherein the patterned sacrificial layers have first sides and second sides opposite to the first sides, the conductive layers include first side conductive layers corresponding to the first sides and second side conductive layers corresponding to the second sides; wherein the interlayer connectors are electrically connected and directly contact corresponding ones of the conductive layers, and the first direction, the second direction, and the third direction are crossed.

Abstract: A neuromorphic computing device includes synapse weights. The synapse weights have different weight values resulted from different transistor arrangements of the synapse weights.

Abstract: A neuromorphic computing device includes first neural circuits, second neural circuits and synapse weights. The first neural circuits are disposed in a first neural region. The second neural circuits are disposed in a second neural region. The synapse weights are electrically connected between the first neural circuits and the second neural circuits, and disposed in a synapse region. The first neural region and the second neural region are on opposing sides of the synapse region respectively.

Abstract: A resistor circuit, an artificial intelligence chip and a method for manufacturing the same are provided. The resistor circuit includes a stack structure. The stack structure includes resistive material layers and insulating layers stacked alternately. The resistor circuit includes at least two unit resistors electrically connected in series or parallel. The at least two unit resistors are respectively defined in the resistive material layers of different layers.

Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

Abstract: A semiconductor device and a method for forming such are provided, the device including: a substrate, a plurality of parallel active semiconductor patterns that extend through a drain-side region and a source-side region, a metal drain contact in the drain-side region, an active gate pattern, a first dummy gate pattern, and a second dummy gate pattern that all extend across the active semiconductor patterns, and a metal interconnect structure located in a region between the first and the second dummy gate patterns. The active semiconductor patterns are doped with a dopant in portions exposed by the dummy gates in dummy gate regions that include the gate cut regions of the first and second dummy gate patterns. The metal interconnect structure connects each of a second subset of the active semiconductor patterns to a respective at least one of a first subset of the active semiconductor patterns.

Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.