Abstract: A memory device includes a common gate input buffer circuit. The input buffer circuit includes an input node configured to receive a signal representative of data to be stored in the memory device and a voltage reference node. The input buffer circuit further includes an amplification circuit electrically coupled to the input node and to the voltage reference node and configured to amplify the signal to provide for an amplified signal. The input buffer circuit additionally includes an equalization circuit electrically coupled to the amplification circuit and configured to process the amplified signal to provide for a filtered signal and an output circuit electrically coupled to equalization circuit and configured to provide for at least one output signal based on the filtered signal, wherein the output signal comprises a differential output signal and wherein the common gate input buffer circuit does not include a common mode feedback (CMFB) loop.

Abstract: A memory device includes a common gate input buffer circuit. The input buffer circuit includes an input node configured to receive a signal representative of data to be stored in the memory device and a voltage reference node. The input buffer circuit further includes an amplification circuit electrically coupled to the input node and to the voltage reference node and configured to amplify the signal to provide for an amplified signal. The input buffer circuit additionally includes an equalization circuit electrically coupled to the amplification circuit and configured to process the amplified signal to provide for a filtered signal and an output circuit electrically coupled to equalization circuit and configured to provide for at least one output signal based on the filtered signal, wherein the output signal comprises a differential output signal and wherein the common gate input buffer circuit does not include a common mode feedback (CMFB) loop.

Abstract: A device and method for detecting the number of revolutions of a sensorless electric park brake (EPB) motor. The device for detecting the number of revolutions of a sensorless motor includes: an actuator driving motor used to set and release a parking brake of an EPB system; an electronic control module for controlling the motor, a vehicle battery for supplying power to the motor and the electronic control module; and a main processing unit for receiving an output signal of the electronic control module and estimating the number of revolutions of the motor, wherein the electronic control module further includes a ripple measuring unit for receiving an output signal of the motor and measuring a ripple of the motor.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A device and method for detecting the number of revolutions of a sensorless electric park brake (EPB) motor. The device for detecting the number of revolutions of a sensorless motor includes: an actuator driving motor used to set and release a parking brake of an EPB system; an electronic control module for controlling the motor, a vehicle battery for supplying power to the motor and the electronic control module; and a main processing unit for receiving an output signal of the electronic control module and estimating the number of revolutions of the motor, wherein the electronic control module further includes a ripple measuring unit for receiving an output signal of the motor and measuring a ripple of the motor.

Abstract: A system for controlling the positions of a caliper and a cable of an electric parking brake (EPB) includes: an actuator driving motor used for engaging and disengaging a parking brake of an EPB system; an electronic control module for controlling the motor; and a vehicle battery for supplying power to the motor and the electronic control module, wherein the electronic control module includes a ripple measuring unit for measuring the ripple of the motor by receiving an output signal of the motor and a current measuring unit for measuring a change in the driving current of the motor.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Abstract: A filter circuit includes a filtering unit configured to filter an input signal and generate an output signal, and a weight generation unit configured to monitor a variation of the output signal and generate weight information based on the monitored variation.

Abstract: An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.

Abstract: A semiconductor integrated circuit can include a reference voltage pad that can be configured to receive an external reference voltage and supply the external reference voltage to the inside of the semiconductor integrated circuit, an internal reference voltage generator that can be configured to generate an internal reference voltage by voltage dividing, a selector that can be configured to select and output one of the external reference voltage and the internal reference voltage in response to a selection signal, and a voltage trimming block that can be configured to regulate the level of the output voltage from the selector in response to trimming signals and outputs the level-regulated voltage as a reference voltage.

Abstract: A filter circuit includes a filtering unit configured to filter an input signal and generate an output signal, and a weight generation unit configured to monitor a variation of the output signal and generate weight information based on the monitored variation.

Abstract: An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.