Abstract: A voltage generating circuit for a semiconductor memory apparatus according includes a data logic voltage generating unit that, when a data output unit outside a semiconductor memory apparatus outputs low-level data, generates an internal data logic voltage at the same potential level as the low-level data in response to an on-die termination signal. In addition, a reference voltage generating circuit for a semiconductor memory apparatus that uses the voltage generating circuit includes a reference voltage generating unit that can be configured to generate a reference voltage at an average potential level between a maximum potential and a minimum potential of input data.

Abstract: A differential amplifier comprises a plurality of first switching elements configured to output differentially amplified signals through output terminals when a voltage level of a first input signal and a second input signal belongs to a first range and a plurality of second switching elements configured to output the differentially amplified signals through the output terminals when the voltage level of the first input signal and the second input signal belongs to a second range.

Abstract: A data transmission circuit includes a data input unit configured to latch data in response to a data strobe signal and to output the data as input data, and a data input timing control unit configured to latch the input data in response to the data strobe signal delayed for a predetermined time interval and to output the input data to a bank group as delay data.

Abstract: An input circuit for a semiconductor integrated circuit in which an operational state is constant even when a process condition, a temperature, a voltage, and the like are varied at the time of operation is provided. The input circuit includes a first input unit that performs a first amplifying operation on a potential difference between a reference voltage and an input signal and outputs a result of the amplification, and a second input unit that performs a second amplifying operation on a signal amplified by the first input unit and outputs a result of the amplification.

Abstract: A test circuit includes an output control section for generating a plurality of output buffer control signals in response to a plurality of data masking signals when a test mode signal is activated in read operation; and a data output buffer for masking some of data input and output pins in response to the plurality of output buffer control signals.

Abstract: A test circuit includes an output control section for generating a plurality of output buffer control signals in response to a plurality of data masking signals when a test mode signal is activated in read operation; and a data output buffer for masking some of data input and output pins in response to the plurality of output buffer control signals.

Abstract: A data output driver that reduces signal skew includes a data multiplexer which reduces a load of a path through which a pull-up/pull-down control signal is generated by a logic-combination of a data signal. It also decreases the number of bits of a pull-up/pull-down resistance-adjusting code signal, and outputs a data signal in response to high impedance information. Furthermore, a path of an output circuit is simplified through which a pull-up/pull-down control is generated in response to the data signal output from the data multiplexer.

Abstract: Data externally inputted in series are output aligned in parallel for a prefetch operation by a data alignment circuit. In the prefetch operation, sequential odd numbered data are latched in response to a rising data strobe signal and sequential even numbered data are latched in response to a falling data strobe signal. Thereafter, the data are output aligned only in response to the falling data strobe signal. The number of latch circuits is reduced. The data alignment circuit includes: a first latch unit that latches the data in response to the data strobe signal to output first and second alignment signals that are output aligned to the falling edge of the data strobe signal; and a second latch unit that latches the first and second alignment signals at the falling edge of the data strobe signal to output align third and fourth data alignment signals that are aligned to the falling edge of the data strobe signal.

Abstract: A differential amplifier comprises a plurality of first switching elements configured to output differentially amplified signals through output terminals when a voltage level of a first input signal and a second input signal belongs to a first range and a plurality of second switching elements configured to output the differentially amplified signals through the output terminals when the voltage level of the first input signal and the second input signal belongs to a second range.

Abstract: A semiconductor integrated circuit can include a reference voltage pad that can be configured to receive an external reference voltage and supply the external reference voltage to the inside of the semiconductor integrated circuit, an internal reference voltage generator that can be configured to generate an internal reference voltage by voltage dividing, a selector that can be configured to select and output one of the external reference voltage and the internal reference voltage in response to a selection signal, and a voltage trimming block that can be configured to regulate the level of the output voltage from the selector in response to trimming signals and outputs the level-regulated voltage as a reference voltage.

Abstract: A buffer control circuit, a semiconductor memory device for a memory module including the buffer control circuit, and a control method of the buffer control circuit, in which power consumption can be reduced. The buffer control circuit includes a first control signal generator that generates an internal buffer control signal in response to write latency signals and internal control signals, and a second control signal generator that generates a buffer control signal in response to the internal buffer control signal and a termination control signal. It is therefore possible to reduce unnecessary power consumption incurred by a data input buffer.

Abstract: A semiconductor memory system which can integrate a plurality of ranks without occupying an increased area. The semiconductor memory system includes a memory device that has a plurality of ranks each having banks integrated therein, and a shared circuit section that is integrated in the memory device and is shared by the plurality of ranks. The plurality of ranks are selectively operated based on the signals provided from the shared circuit section.

Abstract: A voltage generating circuit for a semiconductor memory apparatus according includes a data logic voltage generating unit that, when a data output unit outside a semiconductor memory apparatus outputs low-level data, generates an internal data logic voltage at the same potential level as the low-level data in response to an on-die termination signal. In addition, a reference voltage generating circuit for a semiconductor memory apparatus that uses the voltage generating circuit includes a reference voltage generating unit that can be configured to generate a reference voltage at an average potential level between a maximum potential and a minimum potential of input data.

Abstract: A data output driver that reduces signal skew includes a data multiplexer which reduces a load of a path through which a pull-up/pull-down control signal is generated by a logic-combination of a data signal. It also decreases the number of bits of a pull-up/pull-down resistance-adjusting code signal, and outputs a data signal in response to high impedance information. Furthermore, a path of an output circuit is simplified through which a pull-up/pull-down control is generated in response to the data signal output from the data multiplexer.

Abstract: Data externally inputted in series are output aligned in parallel for a prefetch operation by a data alignment circuit. In the prefetch operation, sequential odd numbered data are latched in response to a rising data strobe signal and sequential even numbered data are latched in response to a falling data strobe signal. Thereafter, the data are output aligned only in response to the falling data strobe signal. The number of latch circuits is reduced. The data alignment circuit includes: a first latch unit that latches the data in response to the data strobe signal to output first and second alignment signals that are output aligned to the falling edge of the data strobe signal; and a second latch unit that latches the first and second alignment signals at the falling edge of the data strobe signal to output align third and fourth data alignment signals that are aligned to the falling edge of the data strobe signal.

Abstract: An input circuit for a semiconductor integrated circuit in which an operational state is constant even when a process condition, a temperature, a voltage, and the like are varied at the time of operation is provided. The input circuit includes a first input unit that performs a first amplifying operation on a potential difference between a reference voltage and an input signal and outputs a result of the amplification, and a second input unit that performs a second amplifying operation on a signal amplified by the first input unit and outputs a result of the amplification.

Abstract: A refresh control circuit for use in a semiconductor memory device having a plurality of banks, including: a bank number signal generator for generating a plurality of bank number signals having a predetermined delay time between generation timings of the plurality of bank number signals based on a refresh signal and a reference signal; and a bank selection unit for generating a plurality of bank selection signals in response to the plurality of bank number signals and a piled-refresh control signals to thereby refresh the plurality of banks.

Abstract: A refresh control circuit for use in a semiconductor memory device having a plurality of banks, including: a bank number signal generator for generating a plurality of bank number signals having a predetermined delay time between generation timings of the plurality of bank number signals based on a refresh signal and a reference signal; and a bank selection unit for generating a plurality of bank selection signals in response to the plurality of bank number signals and a piled-refresh control signals to thereby refresh the plurality of banks.

Abstract: A refresh control circuit for use in a semiconductor memory device having a plurality of banks, including: a bank number signal generator for generating a plurality of bank number signals having a predetermined delay time between generation timings of the plurality of bank number signals based on a refresh signal and a reference signal; and a bank selection unit for generating a plurality of bank selection signals in response to the plurality of bank number signals and a piled-refresh control signals to thereby refresh the plurality of banks.

Abstract: A synchronous memory device can reduce unnecessary current consumption in its operation. In the synchronous memory device, a clock receiver receives an external clock to output a first internal clock. An address latch unit receives and latches an address in synchronous with the first internal clock. A row address latch unit latches a row address that is outputted from the address latch unit. A column address control unit receives the first internal clock to output a second internal clock and stops the output of the second internal clock when a non-column command is performed. Finally, a column address control unit is activated in response to the second internal clock to count a column address that is outputted from the address latch unit so as to output an inner column address.