Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A shower head structure and a plasma processing apparatus are provided. The shower head structure includes a plate body with a first zone and a second zone on a first surface. A plurality of first through holes are in the first zone, each of the first through holes having a diameter uniform with others of the first through holes. A plurality of second through holes are in the second zone. The first zone is in connection with the second zone, and the diameter of each of the first through holes is greater than a diameter of each of the second through holes. A plasma processing apparatus includes the shower head structure is also provided.

Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.

Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Abstract: Methods of amplifying and determining a target nucleotide sequence are provided. The method of amplifying the target nucleotide sequence includes the following steps. A first adaptor and a second adaptor are linked to two ends of a double-stranded nucleic acid molecule with a target nucleotide sequence respectively to form a nucleic acid template, in which the first adaptor includes a Y-form adaptor or a hairpin adaptor and the second adaptor is a hairpin adaptor. Then, a PCR amplification cycle is performed on the nucleic acid template to obtain a PCR amplicon of the target nucleotide sequence.

Abstract: A conjugate cam reducer includes input and output units disposed at two opposite sides of a transmission unit. The transmission unit includes smaller-diameter and larger-diameter cam discs axially connected with each other. The smaller-diameter and larger-diameter cam discs have first and second grooves. The input unit includes an input disc, an eccentric shaft and a plurality of input rollers. The input disc has a smaller inner peripheral wall engaging with the smaller-diameter cam disc, and a plurality of first receiving grooves registered with the first grooves to receive the input rollers. The eccentric shaft is rotated to drive rotation of the transmission unit in an eccentric cycloidal motion. The output unit includes an output disc having a larger inner peripheral wall which engages with the larger-diameter cam disc, and a plurality of second receiving grooves which are registered with the second grooves to receive a plurality of output rollers.

Abstract: A plasma-exclusion-zone ring for a substrate processing system that is configured to process a substrate includes a ring-shaped body, an upper portion of the ring-shaped body, a base and a plasma-exclusion-zone ring notch. The upper portion of the ring-shaped body defines a radially inner surface and a top surface. The base of the ring-shaped body defines a radially outer surface, a first bottom surface extending radially inward from the radially outer surface, and a second bottom surface extending radially inward from the first bottom surface. The plasma-exclusion-zone ring notch is proportional to an alignment notch of the substrate. The first bottom surface is tapered and extends at an acute angle from the second bottom surface to the radially outer surface. The first bottom surface is configured to extend over and oppose a periphery of the substrate.

Abstract: This invention provides processes for treating a mixture of produced water and blowdown water comprising introducing produced water (PW) into blowdown water (BD) for forming a PW-BD water mixture, softening the PW-BD water mixture, subjecting the PW-BD water mixture to activated carbon filtration and reverse osmosis membrane desalination. The process generates a product water and a brine by-product.

Abstract: The present invention relates to a composition of subunit dengue vaccine comprising a fusion protein of conjugating or connecting delta C nonstructural protein 1 (NS1?C or truncated NS1?C) to at least one polypeptides of NS3c (or truncated NS3c) and/or consensus envelope protein domain III (cEDIII), thereby enhancing better protection against DENV challenge and alleviating associated pathological effects.

Abstract: Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.

Abstract: There is provided a time of flight sensor including a light source, a first pixel, a second pixel and a processor. The first pixel generates a first output signal without receiving reflected light from an external object illuminated by the light source. The second pixel generates a second output signal by receiving the reflected light from the external object illuminated by the light source. The processor calculates deviation compensation and deviation correction associated with temperature variation according to the first output signal to accordingly calibrate a distance calculated according to the second output signal.

Abstract: A method and an apparatus for decoding polar codes, the method comprising: determining a starting level for processing an overflow according to a number of encoded bits of a received polar encoded codeword, an input bit-width, and an internal bit-width of a decoder; multiplying an output Log-Likelihood Ratio (LLR) value and two input LLR values of the G function by a first coefficient and a second coefficient respectively; and finally, the LLR values corresponding to the received codeword are decoded to obtain decoded bits.

Abstract: There is provided a time of flight sensor including a light source, a first pixel, a second pixel and a processor. The first pixel generates a first output signal without receiving reflected light from an external object illuminated by the light source. The second pixel generates a second output signal by receiving the reflected light from the external object illuminated by the light source. The processor calculates deviation compensation and deviation correction associated with temperature variation according to the first output signal to accordingly calibrate a distance calculated according to the second output signal.

Abstract: A transceiving device includes a calibration signal generation unit, a phase adjusting unit, a transmission unit, a receiving unit, and a calibration unit. In a calibration mode, the calibration signal generation unit generates an in-phase (I) test signal and a quadrature (Q) test signal. The phase adjusting unit adjusts the I test signal and the Q test signal to generate an adjusted I test signal and an adjusted Q test signal according to a phase controlling signal. The transmission unit generates a radio frequency (RF) signal according to the adjusted I test signal and the adjusted Q test signal. The receiving unit receives the RF signal so as to generate an I receiving signal and a Q receiving signal. The calibration unit generates the phase controlling signal according to the I test signal, the Q test signal, the I receiving signal, and the Q receiving signal.

Abstract: The present invention relates to a biodegradable nanocomplex. The biodegradable nanocomplex comprises a first electrically charged substance, a charge-redistribution substance, a second electrically charged substance and a carried substance, for holding the carried substance inside. The first electrically charged substance and the carried substance have the same electrical polarity, and the biodegradable nanocomplex has a nonuniformally and positively charge distribution along a radial direction thereof.