Abstract: The present invention is directed to a liquid crystal display apparatus including: a timing circuit for operating a shift register within a timing circuit during a vertical blanking period such that a common signal that has been alternated at a cycle of a Single Horizontal period is applied on counter electrodes during the vertical blanking period and such that a storage electrode signal is applied on storage electrodes having a frequency, phase and amplitude identical to those of the common signal.

Abstract: The present invention is directed to a liquid crystal display apparatus including: a timing circuit for operating a shift register within a timing circuit during a vertical blanking period such that a common signal that has been alternated at a cycle of a Single Horizontal period is applied on counter electrodes during the vertical blanking period and such that a storage electrode signal is applied on storage electrodes having a frequency, phase and amplitude identical to those of the common signal.

Abstract: A liquid crystal display device having transistors disposed at the intersections of gate lines and source lines, pixel electrodes connected with the transistors, opposite electrodes opposite to these pixel electrodes, and liquid crystal held between said opposite electrodes and said pixel electrodes is disclosed. The pixel electrodes comprise a first pixel electrode and a second pixel electrode. The second pixel electrode are disposed in a layer above an insulating layer which is itself disposed in a layer above the first pixel electrode. The second pixel electrode has a region that does not overlap with the first pixel electrode. The second pixel electrode are electrically connected with the first pixel electrode.

Abstract: The present invention discloses a liquid crystal display apparatus comprising: a first pixel including a gate electrode extended forming a predetermined angle &thgr; to the scanning line; a drain electrode provided having a portion to be superposed on the gate electrode in a first predetermined region on the signal line side in the gate electrode; a source electrode provided in a second predetermined region opposite to the drain electrode in the gate electrode; a second pixel including a gate electrode extended forming the predetermined angle &thgr; to the scanning line; a source electrode provided having a portion to be superposed on the gate electrode in a third predetermined region on the scanning line side in the gate electrode; and a drain electrode provided in a fourth predetermined region opposite to the source in the gate electrode.