Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240061610
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA
  • Publication number: 20240061574
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 22, 2024
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20240045619
    Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 8, 2024
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Patent number: 11893237
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: February 6, 2024
    Assignee: Kioxia Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 11893238
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: February 6, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
  • Publication number: 20240036769
    Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Patent number: 11886727
    Abstract: According to one embodiment, a controller constructs a plurality of block groups. The plurality of block groups include at least a first block group configured using a first type block group and a second block group configured using a second block group. The first type block group includes a plurality of non-defective blocks obtained by selecting one or more non-defective blocks in an equal number from each of a plurality of dies or each of a plurality of planes. The second type block group includes a plurality of non-defective blocks. The number of non-defective blocks included in the second type block group is equal to the number of non-defective blocks included in the first type block.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: January 30, 2024
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Naoki Esaka
  • Patent number: 11868246
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in the nonvolatile memory to spaces. The write management area is a unit of an area which manages the number of write. The address translation unit translates a logical address of write data into a physical address of a space corresponding to the write data. The write unit writes the write data to a position indicated by the physical address in the nonvolatile memory. The control unit controls the spaces individually with respect to the nonvolatile memory.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: January 9, 2024
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11868653
    Abstract: According to one embodiment, a memory system stores write data received from a host to a shared write buffer for write destination blocks, acquires first write data for plural pages from the shared write buffer, and writes the first write data to a first write destination block by a first-step write operation. When receiving write data from the host in a state in which an empty region does not exist in the shared write buffer, the memory system discards write data in the shared write buffer in which the first-step write operation has been finished. In a case where the first write data do not exist in the shared write buffer when a second-step write operation of the first write data is to be executed, the memory system transmits a request to acquire the first write data to the host.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: January 9, 2024
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11861197
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Yuki Sasaki, Shinichi Kanno
  • Patent number: 11861202
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Shinichi Kanno
  • Patent number: 11861218
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: January 2, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Publication number: 20230418739
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Application
    Filed: September 13, 2023
    Publication date: December 28, 2023
    Inventors: Shinichi KANNO, Hideki YOSHIDA
  • Patent number: 11853178
    Abstract: According to one embodiment, a storage system includes a first storage including first nonvolatile memories storing data which is corrupted when data is read from the first nonvolatile memories, and a controller which controls the first storage. The controller reads data from a first nonvolatile memory at a first address, and determines that whether the read data is to be written back to the first storage or not.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11853200
    Abstract: According to one embodiment, a controller writes a first data associated with a write request and a first logical address specified by the write request to a first block. The controller updates a logical-to-physical address translation table such that a first physical address indicating a first storage location in the first block in which the first data is written is associated with the first logical address. In response to receiving an invalidation request for invalidating the first data corresponding to the first logical address, the controller acquires, from the logical-to-physical address translation table, the first physical address, and updates a valid data identifier corresponding to a storage location indicated by the first physical address to a value indicating invalidation.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11847318
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 19, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 11847350
    Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: December 19, 2023
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Publication number: 20230401149
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 14, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Yuki SASAKI, Shinichi KANNO, Takahiro KURITA
  • Patent number: 11836381
    Abstract: According to one embodiment, in response to receiving a first namespace create command specifying a first attribution from a host, a controller creates a first namespace having the first attribution and a first logical address range. The first logical address range includes logical addresses. The controller sets each of the logical addresses to an unallocated state in which a physical address of the nonvolatile memory is not mapped, during a first period from a time when receiving a power loss advance notification or when detecting an unexpected power loss until a time when the controller becomes a ready state by resupply of a power to the memory system.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: December 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Shinichi Kanno
  • Publication number: 20230384980
    Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.
    Type: Application
    Filed: August 15, 2023
    Publication date: November 30, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO