Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230267075
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Publication number: 20230266915
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 24, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Yuki SASAKI, Shinichi KANNO
  • Publication number: 20230259453
    Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 17, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Naoki ESAKA
  • Publication number: 20230259308
    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Takehiko KURASHIGE
  • Publication number: 20230259452
    Abstract: According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Applicant: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11726906
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11726707
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writ the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: August 15, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Publication number: 20230251798
    Abstract: According to one embodiment, a memory system retrieves write data from a write buffer of a host, and executes a write operation of writing the write data to a write destination location of a write destination block selected from a plurality of blocks. In a case where a first read command to designate the write data as read target data is received from the host before the write operation is finished such that the write data becomes readable, the memory system executes a read operation including an operation of reading the read target data from the write buffer of the host and an operation of returning the read target data to the host. The memory system prohibits releasing a region in the write buffer where the write data is stored until execution of the first read command is completed.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Patent number: 11720288
    Abstract: According to one embodiment, a memory system detects a first block in which an elapsed time from a time point at which the block has been filled with write data exceeds a first period. The memory system notifies a host of a list of identifiers capable of identifying valid data portions stored in the first block or a list of identifiers capable of identifying all data portions stored in the first block. When receiving, from the host, a first copy request specifying one or more valid data portions stored in the first block as copy target data and specifying the second block group as a copy destination block group, the memory system copies the one or more valid data portions specified as the copy target data from the first block to the second block group.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: August 8, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11720487
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: August 8, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Publication number: 20230244383
    Abstract: According to one embodiment, when a command being executed in a nonvolatile memory is an erase/program command and either a first condition or a second condition is satisfied, a memory system suspends an execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The first condition is that either the number of read commands included in the first command group or a sum of weights associated with the read commands is equal to or greater than a first value. The second condition is that one or more read commands are included in the first command group and a time elapsed from when an execution of the erase/program command is started or resumed becomes equal to or greater than a second value.
    Type: Application
    Filed: September 12, 2022
    Publication date: August 3, 2023
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Yuki SASAKI
  • Publication number: 20230236730
    Abstract: According to one embodiment, in response to receiving, from a host, one or more second type commands, a controller of the storage device maintains the received one or more second type commands in a memory region in the storage device without completing processing of the received one or more second type commands. In response to receiving the first type command from the host, the controller completes processing of a second type command, and transmits a command completion response for the first type command to the host as a first preceding response for the first type command. In response to completion of processing of the first type command, the controller transmits a command completion response for the first type command to the host.
    Type: Application
    Filed: September 12, 2022
    Publication date: July 27, 2023
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Kensaku YAMAGUCHI, Takehiko KURASHIGE, Yuki SASAKI
  • Patent number: 11709597
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: July 25, 2023
    Assignee: Kioxia Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20230229791
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving from a host a write request designating a first address for identifying data to be written, the controller encrypts the data with the first address and a first encryption key, and writes the encrypted data to the nonvolatile memory together with the first address. In response to receiving from the host a read request designating a physical address indicative of a physical storage location of the nonvolatile memory, the controller reads both the encrypted data and the first address from the nonvolatile memory on the basis of the physical address, and decrypts the read encrypted data with the first encryption key and the read first address.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 20, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Patent number: 11704019
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
  • Patent number: 11704069
    Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Koichi Nagai
  • Patent number: 11704021
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Shinichi Kanno
  • Publication number: 20230221886
    Abstract: According to one embodiment, a memory system stores write data received from a host to a shared write buffer for write destination blocks, acquires first write data for plural pages from the shared write buffer, and writes the first write data to a first write destination block by a first-step write operation. When receiving write data from the host in a state in which an empty region does not exist in the shared write buffer, the memory system discards write data in the shared write buffer in which the first-step write operation has been finished. In a case where the first write data do not exist in the shared write buffer when a second-step write operation of the first write data is to be executed, the memory system transmits a request to acquire the first write data to the host.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 13, 2023
    Applicant: Kioxia Corporation
    Inventor: Shinichi KANNO
  • Patent number: 11698757
    Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: July 11, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11693770
    Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Naoki Esaka